mb/ocp/sonorapass: Populate FSP-M parameters

Since CPX FSP headers are not released yet, populate certain
settings with hard-coded offsets. Provided values are probably
not correct and I do not understand what they mean and there is
no documentation available yet. However they were found to work
to a certain degree.

TEST=tested on OCP Sonora Pass EVT

Change-Id: I0f78cde69cb8a49a388a412b97bf8713e5b380ea
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40554
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Andrey Petrov 2020-04-20 17:20:23 -07:00 committed by Andrey Petrov
parent 6468d87dde
commit ed7d91d257
2 changed files with 29 additions and 0 deletions

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@ -1 +1,2 @@
bootblock-y += bootblock.c
romstage-y += romstage.c

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@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
void *start = (void *) m_cfg;
// BoardId
*((uint8_t *) (start + 140)) = 0x1d;
// BoardTypeBitmask
*((uint32_t *) (start + 104)) = 0x11111111;
// DebugPrintLevel
*((uint8_t *) (start + 45)) = 8;
// KtiLinkSpeedMode
*((uint8_t *) (start + 64)) = 0;
// mmiolSize
*((uint32_t *) (start + 88)) = 0;
// mmiohBase
*((uint32_t *) (start + 92)) = 0x2000;
// KtiPrefetchEn
*((uint8_t *) (start + 53)) = 2;
// KtiFpgaEnable
*((uint8_t *) (start + 55)) = 0;
*((uint8_t *) (start + 56)) = 0;
}