From ed84a8f5406e35a6f5c88ac30ee003e62f264a14 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 6 Apr 2015 13:51:46 -0700 Subject: [PATCH] rockchip/rk3288: Fix operator precedence error in LPDDR init Upstream coreboot regularly runs Coverity over the code base. Turns out that's a good idea since it's really easy to screw yourself over with a missing parenthesis and some unfortunately deceptive line breaking. This patch fixes a bug in LPDDR3 initialization due to an incorrect operator precedence assumption ( ?: does not bind stronger than | ). In effect, instead of setting MR11[1:0] to 0b11 or 0b00 based on ODT, we're unconditionally setting MR0[1:0] to 0b11. Thankfully, MR0[1:0] seems to contain read-only bits so this might have not been a problem when ODT is off (which is currently true for all LPDDR boards). Also adding a redundant LPDDR_OP() around the 0 to make the intent clearer and changing 3 and 0 to 0x3 and 0x0 to make it more obvious that these are bit masks (right?). BRANCH=veyron BUG=None TEST=Running reboot loop on a Minnie, looks good so far... Change-Id: I06464aaa57e693b1973846a5771162244f7a1c57 Signed-off-by: Patrick Georgi Found-by: Coverity Scan Original-Commit-Id: 5bd9eba39fb7b0f940fead963bbc1878b031b2cb Original-Change-Id: I701ce059472078b5de09a45dd31f54b65a51e641 Original-Signed-off-by: Julius Werner Original-Reviewed-on: https://chromium-review.googlesource.com/264135 Original-Reviewed-by: David Hendricks Original-Reviewed-by: Jinkun Hong Original-Tested-by: Jinkun Hong Reviewed-on: http://review.coreboot.org/9911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/rockchip/rk3288/sdram.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index e7d33ea3a6..0fe2638152 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -1048,8 +1048,8 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) udelay(10); send_command(ddr_pctl_regs, (sdram_params->ch[channel].rank | 1), - MRS_CMD, LPDDR2_MA(11) | - sdram_params->odt ? LPDDR2_OP(3) : 0); + MRS_CMD, LPDDR2_MA(11) | (sdram_params->odt ? + LPDDR2_OP(0x3) : LPDDR2_OP(0x0))); if (channel == 0) { write32(&ddr_pctl_regs->mrrcfg0, 0); send_command(ddr_pctl_regs, 1, MRR_CMD,