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mb/intel/adlrvp: Enable HECI1 communication 

The patch enables HECI1 interface to allow OS applications to communicate
with CSE.

BUG=None
TEST=Build and boot ADLRVP. Run lspci and check pcie device (00:16.0)

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I34ff842481bdfc7933a76555ff0fd70f4fbbb9a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This commit is contained in:
Sridhar Siricilla 2021-04-07 10:18:43 +05:30 committed by Patrick Georgi
parent 09446778e8
commit edc6da2de9
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/intel/adlrvp/devicetree.cb
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@ -12,6 +12,9 @@ chip soc/intel/alderlake
register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E" register "pmc_gpe0_dw2" = "GPP_E"
# Enable HECI1 interface
register "HeciEnabled" = "1"
# FSP configuration # FSP configuration
# Enable CNVi BT # Enable CNVi BT