Add support for the LiPPERT Cool SpaceRunner-LX embedded PC board:
- PC/104+ form factor - AMD Geode-LX CPU/northbridge - AMD CS5536 southbridge - ITE IT8712F Super I/O Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jens Rottmann
Uwe Hermann
parent
6a4bf9886a
commit
edc7ef2b76
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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##
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## Compute the location and size of where this firmware image
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## (coreboot plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
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else
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default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The coreboot bootloader.
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##
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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##
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## Compute where this copy of coreboot will start in the boot rom
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##
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default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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##
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## Compute a range of ROM that can cached to speed up coreboot,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE = 64 * 1024
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default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_PIRQ_TABLE
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object irq_tables.o
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end
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if USE_DCACHE_RAM
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# compile cache_as_ram.c to auto.inc
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makerule ./cache_as_ram_auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an ID string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of coreboot startup.
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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# mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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if USE_DCACHE_RAM
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mainboardinit cpu/amd/model_lx/cache_as_ram.inc
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mainboardinit ./cache_as_ram_auto.inc
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end
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##
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## Include the secondary configuration files
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##
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dir /pc80
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config chip.h
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# See also SMC_CONFIG in cache_as_ram_auto.c.
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# Bit0 turns off Live LED, bit1 switches Com1 to RS485, bit2 same for Com2.
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register "sio_gp1x_config" = "0x01"
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chip northbridge/amd/lx
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device pci_domain 0 on
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device pci 1.0 on end # Northbridge
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device pci 1.1 on end # Graphics
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device pci 1.2 on end # AES
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chip southbridge/amd/cs5536
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# IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
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# SIRQ Mode = Active(Quiet) mode. Save power....
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
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# UARTs, etc IRQs. OK
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register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010
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register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above
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register "lpc_serirq_mode" = "1"
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register "enable_gpio_int_route" = "0x0D0C0700"
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register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
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register "enable_USBP4_device" = "0" # 0:host, 1:device
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register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
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register "com1_enable" = "0"
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register "com1_address" = "0x3E8"
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register "com1_irq" = "6"
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register "com2_enable" = "0"
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register "com2_address" = "0x2E8"
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register "com2_irq" = "6"
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register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8
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register "unwanted_vpci[1]" = "0" # End of list has a zero
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device pci 8.0 on end # Slot4
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device pci 9.0 on end # Slot3
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device pci a.0 on end # Slot2
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device pci b.0 on end # Slot1
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device pci c.0 on end # IT8888
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device pci e.0 on end # Ethernet
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device pci f.0 on # ISA Bridge
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chip superio/ite/it8712f
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 on # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # EC
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io 0x60 = 0x290
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io 0x62 = 0x230
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irq 0x70 = 9
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end
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device pnp 2e.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.6 on # PS/2 mouse
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irq 0x70 = 12
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end
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device pnp 2e.7 on # GPIO
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io 0x62 = 0x1220
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io 0x64 = 0x1200
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end
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device pnp 2e.8 off # MIDI
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io 0x60 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.9 off # Game port
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io 0x60 = 0x220
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end
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device pnp 2e.a off end # CIR
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end
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end
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device pci f.2 on end # IDE
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device pci f.3 off end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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# APIC cluster is late CPU init.
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device apic_cluster 0 on
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chip cpu/amd/model_lx
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device apic 0 on end
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end
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end
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end
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@ -0,0 +1,209 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HAVE_OPTION_TABLE
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uses USE_OPTION_TABLE
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_IDE
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uses CONFIG_FS_PAYLOAD
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uses CONFIG_FS_EXT2
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uses AUTOBOOT_DELAY
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uses AUTOBOOT_CMDLINE
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uses IRQ_SLOT_COUNT
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses COREBOOT_EXTRA_VERSION
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uses ARCH
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uses FALLBACK_SIZE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_COMPRESS
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uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses _RAMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses HAVE_MP_TABLE
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses DEBUG
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_VIDEO_MB
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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uses PIRQ_ROUTE
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 512*1024
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###
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### Build options
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###
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default CONFIG_CONSOLE_VGA = 0
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default CONFIG_VIDEO_MB = 8
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default CONFIG_PCI_ROM_RUN = 0
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT = 1
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##
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## no MP table
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##
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default HAVE_MP_TABLE = 0
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##
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## Build code to reset the motherboard from coreboot
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##
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default HAVE_HARD_RESET = 0
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## Delay timer options
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##
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE = 1
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default IRQ_SLOT_COUNT = 7
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default PIRQ_ROUTE = 1
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE = 0
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###
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### coreboot layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
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default ROM_IMAGE_SIZE = 64 * 1024
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default FALLBACK_SIZE = 128 * 1024
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##
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## enable CACHE_AS_RAM specifics
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##
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default USE_DCACHE_RAM = 1
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default DCACHE_RAM_BASE = 0xc8000
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default DCACHE_RAM_SIZE = 0x08000
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##
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## Use a small 8K stack
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##
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default STACK_SIZE = 0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE = 0x4000
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##
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## Only use the option table in a normal image
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##
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#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
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default CONFIG_ROM_PAYLOAD = 1
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##
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## The default compiler
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##
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default CROSS_COMPILE = ""
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default CC = "$(CROSS_COMPILE)gcc -m32"
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default HOSTCC = "gcc"
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##
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## The Serial Console
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##
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250 = 1
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## Select the serial console baud rate
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default TTYS0_BAUD = 115200
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#default TTYS0_BAUD = 57600
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#default TTYS0_BAUD = 38400
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#default TTYS0_BAUD = 19200
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#default TTYS0_BAUD = 9600
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#default TTYS0_BAUD = 4800
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#default TTYS0_BAUD = 2400
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#default TTYS0_BAUD = 1200
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# Select the serial console base port
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default TTYS0_BASE = 0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS = 0x3
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# Compile extra debugging code
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default DEBUG = 1
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##
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### Select the coreboot loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL = 8
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## At a maximum only compile in this level of debugging
|
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default MAXIMUM_CONSOLE_LOGLEVEL = 8
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end
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@ -0,0 +1,235 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2008 LiPPERT Embedded Computers GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
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#define ASSEMBLY 1
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#include <stdlib.h>
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#include <stdint.h>
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#include <spd.h>
|
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#include <device/pci_def.h>
|
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/lxdef.h>
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#include <cpu/amd/geode_post_code.h>
|
||||
#include "southbridge/amd/cs5536/cs5536.h"
|
||||
|
||||
#define POST_CODE(x) outb(x, 0x80)
|
||||
|
||||
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
|
||||
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
|
||||
#include "superio/ite/it8712f/it8712f_early_serial.c"
|
||||
|
||||
/* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */
|
||||
#define SMC_CONFIG 0x01
|
||||
|
||||
#define ManualConf 1 /* No automatic strapped PLL config */
|
||||
#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */
|
||||
#define PLLMSRlo 0x00DE6001
|
||||
#define DIMM0 0xA0
|
||||
#define DIMM1 0xA2
|
||||
|
||||
static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I
|
||||
0xFF, 0xFF, // only values used by Geode-LX raminit.c are set
|
||||
[SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type
|
||||
[SPD_NUM_ROWS] = 0x0D, // Number of row address bits [13]
|
||||
[SPD_NUM_COLUMNS] = 0x0A, // Number of column address bits [10]
|
||||
[SPD_NUM_DIMM_BANKS] = 1, // Number of module rows (banks)
|
||||
0xFF, 0xFF, 0xFF,
|
||||
[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x50, // SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [5.0 ns in BCD]
|
||||
0xFF, 0xFF,
|
||||
[SPD_REFRESH] = 0x82, // Refresh rate/type [Self Refresh, 7.8 us]
|
||||
[SPD_PRIMARY_SDRAM_WIDTH] = 64, // SDRAM width (primary SDRAM) [64 bits]
|
||||
0xFF, 0xFF, 0xFF,
|
||||
[SPD_NUM_BANKS_PER_SDRAM] = 4, // SDRAM device attributes, number of banks on SDRAM device
|
||||
[SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, // SDRAM device attributes, CAS latency [3, 2.5, 2]
|
||||
0xFF, 0xFF,
|
||||
[SPD_MODULE_ATTRIBUTES] = 0x20, // SDRAM module attributes [differential clk]
|
||||
[SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, // SDRAM device attributes, general [Concurrent AP]
|
||||
[SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, // SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD]
|
||||
0xFF,
|
||||
[SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, // SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD]
|
||||
0xFF,
|
||||
[SPD_tRP] = 60, // Min. row precharge time [15 ns in units of 0.25 ns]
|
||||
[SPD_tRRD] = 40, // Min. row active to row active [10 ns in units of 0.25 ns]
|
||||
[SPD_tRCD] = 60, // Min. RAS to CAS delay [15 ns in units of 0.25 ns]
|
||||
[SPD_tRAS] = 40, // Min. RAS pulse width = active to precharge delay [40 ns]
|
||||
[SPD_BANK_DENSITY] = 0x40, // Density of each row on module [256 MB]
|
||||
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
[SPD_tRFC] = 70 // SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [70 ns]
|
||||
};
|
||||
|
||||
static inline int spd_read_byte(unsigned int device, unsigned int address)
|
||||
{
|
||||
if (device != DIMM0)
|
||||
return 0xFF; /* No DIMM1, don't even try. */
|
||||
|
||||
#if DEBUG
|
||||
if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
|
||||
print_err("ERROR: spd_read_byte(DIMM0, 0x");
|
||||
print_err_hex8(address);
|
||||
print_err(") returns 0xff\r\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Fake SPD ROM value */
|
||||
return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF;
|
||||
}
|
||||
|
||||
/* Send config data to System Management Controller via SMB. */
|
||||
static int smc_send_config(unsigned char config_data)
|
||||
{
|
||||
if (smbus_check_stop_condition(SMBUS_IO_BASE))
|
||||
return 1;
|
||||
if (smbus_start_condition(SMBUS_IO_BASE))
|
||||
return 2;
|
||||
if (smbus_send_slave_address(SMBUS_IO_BASE, 0x50)) // SMC address
|
||||
return 3;
|
||||
if (smbus_send_command(SMBUS_IO_BASE, 0x28)) // set config data
|
||||
return 4;
|
||||
if (smbus_send_command(SMBUS_IO_BASE, 0x01)) // data length
|
||||
return 5;
|
||||
if (smbus_send_command(SMBUS_IO_BASE, config_data))
|
||||
return 6;
|
||||
smbus_stop_condition(SMBUS_IO_BASE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#include "northbridge/amd/lx/raminit.h"
|
||||
#include "northbridge/amd/lx/pll_reset.c"
|
||||
#include "northbridge/amd/lx/raminit.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
#include "cpu/amd/model_lx/cpureginit.c"
|
||||
#include "cpu/amd/model_lx/syspreinit.c"
|
||||
|
||||
static void msr_init(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
/* Setup access to the cache for under 1MB. */
|
||||
msr.hi = 0x24fffc02;
|
||||
msr.lo = 0x1000A000; /* 0-A0000 write back */
|
||||
wrmsr(CPU_RCONF_DEFAULT, msr);
|
||||
|
||||
msr.hi = 0x0; /* Write back */
|
||||
msr.lo = 0x0;
|
||||
wrmsr(CPU_RCONF_A0_BF, msr);
|
||||
wrmsr(CPU_RCONF_C0_DF, msr);
|
||||
wrmsr(CPU_RCONF_E0_FF, msr);
|
||||
|
||||
/* Setup access to the cache for under 640K. Note MC not setup yet. */
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU0 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU0 + 0x21, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU1 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU1 + 0x21, msr);
|
||||
}
|
||||
|
||||
static const u16 sio_init_table[] = { // hi=data, lo=index
|
||||
0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...)
|
||||
0x1E2C, // disable ATXPowerGood
|
||||
0x0423, // don't delay POWerOK1/2
|
||||
0x9072, // watchdog triggers POWOK, counts seconds
|
||||
#if !USE_WATCHDOG_ON_BOOT
|
||||
0x0073, 0x0074, // disable watchdog by setting timeout to 0
|
||||
#endif
|
||||
0xBF25, 0x172A, 0xF326, // select GPIO function for most pins
|
||||
0xFF27, 0xDF28, 0x2729, // (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1)
|
||||
0x072C, // VIN6=enabled?, FAN4/5 disabled, VIN7=internal, VIN3=internal
|
||||
0x66B8, 0x0CB9, // enable pullups
|
||||
0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED
|
||||
0x07C8, // config GP12-10 as output
|
||||
0x2DF5, // map Hw Monitor Thermal Output to GP55
|
||||
0x08F8, // map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use)
|
||||
};
|
||||
|
||||
/* Early mainboard specific GPIO setup. */
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
|
||||
it8712f_enter_conf();
|
||||
for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
|
||||
u16 val = sio_init_table[i];
|
||||
outb((u8)val, SIO_INDEX);
|
||||
outb(val >> 8, SIO_DATA);
|
||||
}
|
||||
it8712f_exit_conf();
|
||||
}
|
||||
|
||||
void cache_as_ram_main(void)
|
||||
{
|
||||
int err;
|
||||
POST_CODE(0x01);
|
||||
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
|
||||
};
|
||||
|
||||
SystemPreInit();
|
||||
msr_init();
|
||||
|
||||
cs5536_early_setup();
|
||||
|
||||
/*
|
||||
* Note: Must do this AFTER the early_setup! It is counting on some
|
||||
* early MSR setup for CS5536.
|
||||
*/
|
||||
it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter
|
||||
mb_gpio_init();
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
||||
/* bit1 = on-board IDE is slave, bit0 = Spread Spectrum */
|
||||
if ((err = smc_send_config(SMC_CONFIG))) {
|
||||
print_err("ERROR ");
|
||||
print_err_char('0'+err);
|
||||
print_err(" sending config data to SMC\r\n");
|
||||
}
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Check memory. */
|
||||
/* ram_check(0, 640 * 1024); */
|
||||
|
||||
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 LiPPERT Embedded Computers GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern struct chip_operations mainboard_lippert_spacerunner_lx_ops;
|
||||
|
||||
struct mainboard_lippert_spacerunner_lx_config {
|
||||
/* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */
|
||||
u8 sio_gp1x_config;
|
||||
};
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 LiPPERT Embedded Computers GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include "../../../southbridge/amd/cs5536/cs5536.h"
|
||||
|
||||
/* Platform IRQs */
|
||||
#define PIRQA 10
|
||||
#define PIRQB 11
|
||||
#define PIRQC 5
|
||||
#define PIRQD 15
|
||||
|
||||
/* Map */
|
||||
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
|
||||
|
||||
/* Link */
|
||||
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
|
||||
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
|
||||
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
|
||||
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32 + 16 * IRQ_SLOT_COUNT,/* There can be total 7 devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
|
||||
0x00, /* IRQs devoted exclusively to PCI usage */
|
||||
0x100B, /* Vendor */
|
||||
0x002B, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
|
||||
0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
|
||||
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
|
||||
{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
|
||||
{0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */
|
||||
{0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */
|
||||
{0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */
|
||||
{0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 LiPPERT Embedded Computers GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "chip.h"
|
||||
|
||||
static const u16 ec_init_table[] = { /* hi=data, lo=index */
|
||||
0x1900, /* Enable monitoring */
|
||||
0x3050, /* VIN4,5 enabled */
|
||||
0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
|
||||
0x805C, /* Unlock zero adjust */
|
||||
0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
|
||||
0x005C, /* Lock zero adjust */
|
||||
0xD014 /* Also set FAN_CTL polarity to Active High */
|
||||
};
|
||||
|
||||
static void init(struct device *dev)
|
||||
{
|
||||
struct mainboard_lippert_spacerunner_lx_config *mb = dev->chip_info;
|
||||
unsigned int gpio_base, i;
|
||||
printk_debug("LiPPERT SpaceRunner-LX ENTER %s\n", __FUNCTION__);
|
||||
|
||||
/* Init CS5536 GPIOs */
|
||||
gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
|
||||
PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
|
||||
|
||||
outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
|
||||
outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
|
||||
outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM#
|
||||
outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
|
||||
outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
|
||||
outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
|
||||
outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
|
||||
outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz
|
||||
|
||||
/* Init Environment Controller. */
|
||||
for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
|
||||
u16 val = ec_init_table[i];
|
||||
outb((u8)val, 0x0295);
|
||||
outb(val >> 8, 0x0296);
|
||||
}
|
||||
|
||||
outb(mb->sio_gp1x_config, 0x1220); /* Simple-I/O GP17-10 */
|
||||
printk_debug("LiPPERT SpaceRunner-LX EXIT %s\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
dev->ops->init = init;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_lippert_spacerunner_lx_ops = {
|
||||
CHIP_NAME("LiPPERT SpaceRunner-LX Mainboard")
|
||||
.enable_dev = enable_dev,
|
||||
};
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
# Config file for the LiPPERT Cool SpaceRunner-LX. --JR 10/2008
|
||||
|
||||
target spacerunner-lx
|
||||
mainboard lippert/spacerunner-lx
|
||||
|
||||
# HACK to get the right TSC support.
|
||||
option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
|
||||
option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0
|
||||
option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0
|
||||
|
||||
## Load payload (e.g. Linux) from IDE.
|
||||
#option CONFIG_ROM_PAYLOAD = 0
|
||||
#option CONFIG_IDE = 1
|
||||
#option CONFIG_FS_PAYLOAD = 1
|
||||
#option CONFIG_FS_EXT2 = 1
|
||||
#option AUTOBOOT_DELAY = 0
|
||||
#option AUTOBOOT_CMDLINE = "hda1:/payload.elf"
|
||||
|
||||
# Leave 36k for VSA. Board is equipped with a 1 MB SPI flash, however, due to
|
||||
# limitations of the IT8712F Super I/O, only the top 512 KB are directly mapped.
|
||||
option ROM_SIZE = (512 * 1024) - (36 * 1024)
|
||||
option FALLBACK_SIZE = ROM_SIZE
|
||||
|
||||
#option DEFAULT_CONSOLE_LOGLEVEL = 4
|
||||
#option MAXIMUM_CONSOLE_LOGLEVEL = 4
|
||||
|
||||
# Saves space on ROM_IMAGE_SIZE, but decompression costs a second on boot.
|
||||
option CONFIG_COMPRESS = 1
|
||||
|
||||
romimage "image"
|
||||
option USE_FALLBACK_IMAGE = 1
|
||||
option ROM_IMAGE_SIZE = 64 * 1024
|
||||
option COREBOOT_EXTRA_VERSION = ".0"
|
||||
payload ../payload.elf
|
||||
# If getting payload from IDE
|
||||
# payload /dev/null
|
||||
end
|
||||
|
||||
buildrom ./coreboot.rom ROM_SIZE "image"
|
||||
Loading…
Reference in New Issue