mainboard/asus/p3b-f: Reintroduce as variant of p2b
Fold this last ASUS 440BX board into the P2B family, while bringing in some changes: - Devicetree becomes overridetree. - Remove non-existent IR device and disable ACPI device on Super I/O to match OEM firmware. - Add SB GPO settings from OEM firmware to devicetree. This disables the SPD enabling magic this board needs. By moving the enabling part to bootblock the hacky enable_spd hook can be eliminated. - Initialize the serial port in bootblock, like the other boards. Boot tested on hardware. Change-Id: I65f2cb9d1bd4c82550de43889e3502526a46bd18 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41047 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Keith Hui
Patrick Georgi
parent
75476ec303
commit
edd38465a5
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@ -4,7 +4,7 @@
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##
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## SPDX-License-Identifier: GPL-2.0-only
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if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS
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if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F
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config BASE_ASUS_P2B_D
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def_bool n
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@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
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select SUPERIO_WINBOND_W83977TF
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select HAVE_PIRQ_TABLE
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select BOARD_ROMSIZE_KB_256
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select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS
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select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F
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select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS
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select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS
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@ -40,6 +40,7 @@ config MAINBOARD_PART_NUMBER
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default "P2B-DS" if BOARD_ASUS_P2B_DS
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default "P2B-F" if BOARD_ASUS_P2B_F
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default "P2B-LS" if BOARD_ASUS_P2B_LS
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default "P3B-F" if BOARD_ASUS_P3B_F
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config VARIANT_DIR
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string
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@ -48,6 +49,7 @@ config VARIANT_DIR
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default "p2b-ds" if BOARD_ASUS_P2B_DS
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default "p2b-f" if BOARD_ASUS_P2B_F
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default "p2b-ls" if BOARD_ASUS_P2B_LS
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default "p3b-f" if BOARD_ASUS_P3B_F
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config OVERRIDE_DEVICETREE
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string
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@ -55,7 +57,7 @@ config OVERRIDE_DEVICETREE
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config IRQ_SLOT_COUNT
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int
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default 8 if BOARD_ASUS_P2B_LS
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default 8 if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F
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default 7 if BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_DS
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default 6
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@ -12,3 +12,6 @@ config BOARD_ASUS_P2B_F
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config BOARD_ASUS_P2B_LS
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bool "P2B-LS"
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config BOARD_ASUS_P3B_F
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bool "P3B-F"
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@ -1,4 +1,5 @@
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bootblock-y += bootblock.c
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romstage-$(CONFIG_BOARD_ASUS_P3B_F) += variants/$(VARIANT_DIR)/romstage.c
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ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += variants/$(VARIANT_DIR)/irq_tables.c
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ramstage-$(CONFIG_GENERATE_MP_TABLE) += variants/$(VARIANT_DIR)/mptable.c
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@ -0,0 +1,12 @@
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chip northbridge/intel/i440bx # Northbridge
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device domain 0 on # PCI domain
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chip southbridge/intel/i82371eb # Southbridge
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register "gpo" = "0x67ffbfff" # GPIO: This value sets GPIOs 27,28 to expose HWM
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device pci 4.0 on # ISA bridge
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chip superio/winbond/w83977tf # Super I/O
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device pnp 3f0.a off end # ACPI
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end
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end
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end
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end
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end
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@ -4,12 +4,6 @@
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#include <arch/io.h>
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#include <southbridge/intel/i82371eb/i82371eb.h>
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#include <northbridge/intel/i440bx/raminit.h>
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#include <superio/winbond/common/winbond.h>
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/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
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#include <superio/winbond/w83977tf/w83977tf.h>
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/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
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#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
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/*
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* ASUS P3B-F specific SPD enable magic.
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@ -41,8 +35,3 @@ void disable_spd(void)
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{
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outb(0x67, PM_IO_BASE + 0x37);
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}
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void mainboard_enable_serial(void)
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{
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -1,31 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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##
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## SPDX-License-Identifier: GPL-2.0-only
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if BOARD_ASUS_P3B_F
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_INTEL_SLOT_1
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select NORTHBRIDGE_INTEL_I440BX
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select SOUTHBRIDGE_INTEL_I82371EB
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select SUPERIO_WINBOND_W83977TF
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select HAVE_PIRQ_TABLE
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select BOARD_ROMSIZE_KB_256
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select SDRAMPWR_4DIMM
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config MAINBOARD_DIR
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string
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default "asus/p3b-f"
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config MAINBOARD_PART_NUMBER
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string
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default "P3B-F"
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config IRQ_SLOT_COUNT
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int
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default 8
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endif # BOARD_ASUS_P3B_F
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@ -1,2 +0,0 @@
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config BOARD_ASUS_P3B_F
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bool "P3B-F"
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@ -1,59 +0,0 @@
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chip northbridge/intel/i440bx # Northbridge
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device lapic 0 on end # APIC
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end
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end
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device domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 4.0 on # ISA bridge
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chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
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device pnp 3f0.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 3f0.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 3f0.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 3f0.3 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 3f0.6 on # Consumer IR
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end
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device pnp 3f0.7 on # GPIO 1
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end
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device pnp 3f0.8 on # GPIO 2
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end
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device pnp 3f0.a on # ACPI
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end
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end
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end
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device pci 4.1 on end # IDE
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device pci 4.2 on end # USB
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device pci 4.3 on end # ACPI
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "ide_legacy_enable" = "1"
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# Enable UDMA/33 for higher speed if your IDE device(s) support it.
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register "ide0_drive0_udma33_enable" = "0"
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register "ide0_drive1_udma33_enable" = "0"
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register "ide1_drive0_udma33_enable" = "0"
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register "ide1_drive1_udma33_enable" = "0"
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end
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end
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end
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