nb/intel/sandybridge: Remove unnecessary comments
These comments were helpful before the massive IOSAV refactoring, but they are no longer needed since the function names are clear enough. Change-Id: Ieb9bdf3f7fc72f63a8978f2b98e0bc8228c55868 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48401 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons
Felix Held
parent
7e439c9a5d
commit
edd7cb4d67
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@ -546,11 +546,7 @@ static void write_reset(ramctr_timing *ctrl)
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iosav_write_zqcs_sequence(channel, slotrank, 3, 8, 0);
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/*
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* Execute command queue - why is bit 22 set here?!
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*
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* This is actually using the IOSAV state machine as a timer, so refresh is allowed.
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*/
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/* This is actually using the IOSAV state machine as a timer */
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iosav_run_queue(channel, 1, 1);
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wait_for_iosav(channel);
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@ -684,7 +680,6 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg,
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};
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iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence));
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/* Execute command queue */
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iosav_run_once(channel);
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}
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@ -895,11 +890,9 @@ void dram_mrscommands(ramctr_timing *ctrl)
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};
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iosav_write_sequence(BROADCAST_CH, zqcl_sequence, ARRAY_SIZE(zqcl_sequence));
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/* Execute command queue on all channels. Do it four times. */
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iosav_run_queue(BROADCAST_CH, 4, 0);
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FOR_ALL_CHANNELS {
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/* Wait for ref drained */
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wait_for_iosav(channel);
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}
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@ -913,15 +906,12 @@ void dram_mrscommands(ramctr_timing *ctrl)
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slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2;
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/* Drain */
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wait_for_iosav(channel);
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iosav_write_zqcs_sequence(channel, slotrank, 4, 101, 31);
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/* Execute command queue */
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iosav_run_once(channel);
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/* Drain */
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wait_for_iosav(channel);
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}
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}
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@ -1062,7 +1052,6 @@ static void test_rcven(ramctr_timing *ctrl, int channel, int slotrank)
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/* Send a burst of 16 back-to-back read commands (4 DCLK apart) */
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iosav_write_read_mpr_sequence(channel, slotrank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -1347,7 +1336,6 @@ int receive_enable_calibration(ramctr_timing *ctrl)
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iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 0);
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/* Execute command queue */
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iosav_run_once(channel);
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const union gdcr_training_mod_reg training_mod = {
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@ -1440,14 +1428,12 @@ static void test_tx_dq(ramctr_timing *ctrl, int channel, int slotrank)
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iosav_write_misc_write_sequence(ctrl, channel, slotrank,
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MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), 4, 4, 500, 18);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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iosav_write_prea_act_read_sequence(ctrl, channel, slotrank);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -1482,7 +1468,6 @@ static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank)
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iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 18);
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/* Execute command queue */
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iosav_run_once(channel);
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for (tx_dq = 0; tx_dq <= MAX_TX_DQ; tx_dq++) {
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@ -1605,7 +1590,6 @@ static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank)
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}
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program_timings(ctrl, channel);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -1686,7 +1670,6 @@ static void train_write_flyby(ramctr_timing *ctrl)
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iosav_write_misc_write_sequence(ctrl, channel, slotrank, 3, 1, 3, 3, 31);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -1757,7 +1740,6 @@ static void train_write_flyby(ramctr_timing *ctrl)
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};
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iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence));
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -1788,7 +1770,6 @@ static void disable_refresh_machine(ramctr_timing *ctrl)
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iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -1869,7 +1850,6 @@ static int jedec_write_leveling(ramctr_timing *ctrl)
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iosav_write_zqcs_sequence(channel, 0, 4, 101, 31);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -1951,7 +1931,6 @@ static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank)
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MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd;
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MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd;
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -2165,7 +2144,6 @@ static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank,
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iosav_write_read_mpr_sequence(
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channel, slotrank, ctrl->tMOD, 500, 4, 1, ctrl->CAS + 8);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -2212,7 +2190,6 @@ static void find_predefined_pattern(ramctr_timing *ctrl, const int channel)
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iosav_write_read_mpr_sequence(
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channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -2233,7 +2210,6 @@ static void find_predefined_pattern(ramctr_timing *ctrl, const int channel)
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iosav_write_read_mpr_sequence(
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channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -2349,7 +2325,6 @@ static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank
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iosav_write_data_write_sequence(ctrl, channel, slotrank);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -2447,7 +2422,6 @@ static void test_aggressive_write(ramctr_timing *ctrl, int channel, int slotrank
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iosav_write_aggressive_write_read_sequence(ctrl, channel, slotrank);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -2629,7 +2603,6 @@ int channel_test(ramctr_timing *ctrl)
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iosav_write_memory_test_sequence(ctrl, channel, slotrank);
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/* Execute command queue */
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iosav_run_once(channel);
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wait_for_iosav(channel);
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@ -2752,7 +2725,6 @@ void channel_scrub(ramctr_timing *ctrl)
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};
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iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence));
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/* Execute command queue */
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iosav_run_queue(channel, 16, 0);
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wait_for_iosav(channel);
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