mb/lenovo/t520: Convert remaining PCI numbers into reference names
Change-Id: I18ce899516fd38b21ded1e3144aa22e705c534b8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79965 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -144,8 +144,8 @@ chip northbridge/intel/sandybridge
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device i2c 5f on end
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device i2c 5f on end
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end
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end
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end # SMBus
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end # SMBus
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device pci 1f.5 off end # IDE controller
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device ref sata2 off end # IDE controller
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device pci 1f.6 off end # Thermal controller
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device ref thermal off end # Thermal controller
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end
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end
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end
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end
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end
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end
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@ -2,7 +2,7 @@ chip northbridge/intel/sandybridge
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register "spd_addresses" = "{0x50, 0, 0x51, 0}"
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register "spd_addresses" = "{0x50, 0, 0x51, 0}"
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device domain 0 on
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device domain 0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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device pci 1f.0 on # LPC bridge
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device ref lpc on # LPC bridge
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chip ec/lenovo/h8
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chip ec/lenovo/h8
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device pnp ff.2 on end # dummy
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device pnp ff.2 on end # dummy
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register "has_wwan_detection" = "1"
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register "has_wwan_detection" = "1"
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@ -2,7 +2,7 @@ chip northbridge/intel/sandybridge
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register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}"
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register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}"
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device domain 0 on
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device domain 0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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device pci 1c.6 on end # PCIe Port #7 USB 3.0
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device ref pcie_rp7 on end # PCIe Port #7 USB 3.0
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end
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end
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end
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end
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end
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end
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