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skylake: Add Deep Sx configuration for wake pins 

Add support for enabling various pins in Deep Sx by setting
a register in the mainboard devicetree.

BUG=chrome-os-partner:43079
BRANCH=none
TEST=build and boot on glados

Original-Change-Id: I1b4fb51f72b88bdc49096268bdd781750dcd089d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288920
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I7555a92fecc6e78b579ec0bc18da202cb0c824e2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11170
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Duncan Laurie 2015-07-24 15:37:13 -07:00 committed by Aaron Durbin
parent 4f7cf3a446
commit edf1cb78e2
3 changed files with 26 additions and 0 deletions
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9
src/soc/intel/skylake/chip.h
View File

@ -21,6 +21,7 @@
#include <stdint.h> #include <stdint.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/serialio.h> #include <soc/serialio.h>
#ifndef _SOC_CHIP_H_ #ifndef _SOC_CHIP_H_
@ -112,6 +113,14 @@ struct soc_intel_skylake_config {
int deep_s3_enable; int deep_s3_enable;
int deep_s5_enable; int deep_s5_enable;
/*
* Deep Sx Configuration
* DSX_EN_WAKE_PIN - Enable WAKE# pin
* DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
* DSX_EN_AC_PRESENT_PIN - Enable AC_PRESENT pin
*/
uint32_t deep_sx_config;
/* TCC activation offset */ /* TCC activation offset */
int tcc_offset; int tcc_offset;

5
src/soc/intel/skylake/include/soc/pmc.h
View File

@ -55,6 +55,11 @@
#define S5_PWRGATE_POL 0x30 #define S5_PWRGATE_POL 0x30
#define S5DC_GATE_SUS (1 << 15) #define S5DC_GATE_SUS (1 << 15)
#define S5AC_GATE_SUS (1 << 14) #define S5AC_GATE_SUS (1 << 14)
#define DSX_CFG 0x34
#define DSX_CFG_MASK 0x7
#define DSX_EN_WAKE_PIN (1 << 2)
#define DSX_EN_AC_PRESENT_PIN (1 << 1)
#define DSX_EN_LAN_WAKE_PIN (1 << 0)
#define PMSYNC_TPR_CFG 0xc4 #define PMSYNC_TPR_CFG 0xc4
#define PMSYNC_LOCK (1 << 31) #define PMSYNC_LOCK (1 << 31)
#define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE0 0x124

12
src/soc/intel/skylake/pmc.c
View File

@ -217,6 +217,17 @@ static void config_deep_s3(int on)
config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS | S3AC_GATE_SUS, 3, on); config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS | S3AC_GATE_SUS, 3, on);
} }
static void config_deep_sx(uint32_t deepsx_config)
{
uint32_t reg;
uint8_t *pmcbase = pmc_mmio_regs();
reg = read32(pmcbase + DSX_CFG);
reg &= ~DSX_CFG_MASK;
reg |= deepsx_config;
write32(pmcbase + DSX_CFG, reg);
}
static void pmc_init(struct device *dev) static void pmc_init(struct device *dev)
{ {
config_t *config = dev->chip_info; config_t *config = dev->chip_info;
@ -231,6 +242,7 @@ static void pmc_init(struct device *dev)
config_deep_s3(config->deep_s3_enable); config_deep_s3(config->deep_s3_enable);
config_deep_s5(config->deep_s5_enable); config_deep_s5(config->deep_s5_enable);
config_deep_sx(config->deep_sx_config);
} }
static struct device_operations device_ops = { static struct device_operations device_ops = {