soc/intel/common/block/acpi: Update northbridge.asl to ASL2.0 syntax
This change updates northbridge.asl to use ASL2.0 syntax. This increases the readability of the ASL code. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: If8eabb6b934b74e69cdf4e18981082028399244d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -183,21 +183,21 @@ Method (_CRS, 0, Serialized)
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* Fix up PCI memory region
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* Start with Top of Lower Usable DRAM
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*/
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Store (\_SB.PCI0.MCHC.TLUD, PMIN)
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Add (Subtract (PMAX, PMIN), 1, PLEN)
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PMIN = \_SB.PCI0.MCHC.TLUD
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PLEN = PMAX - PMIN + 1
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/* Patch PM02 range based on Memory Size */
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If (LEqual (A4GS, 0)) {
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If (A4GS == 0) {
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CreateQwordField (MCRS, PM02._LEN, MSEN)
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Store (0, MSEN)
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MSEN = 0
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} Else {
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CreateQwordField (MCRS, PM02._MIN, MMIN)
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CreateQwordField (MCRS, PM02._MAX, MMAX)
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CreateQwordField (MCRS, PM02._LEN, MLEN)
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/* Set 64bit MMIO resource base and length */
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Store (A4GS, MLEN)
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Store (A4GB, MMIN)
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Subtract (Add (MMIN, MLEN), 1, MMAX)
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MLEN = A4GS
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MMIN = A4GB
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MMAX = MMIN + MLEN - 1
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}
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Return (MCRS)
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@ -206,35 +206,35 @@ Method (_CRS, 0, Serialized)
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/* Get MCH BAR */
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Method (GMHB, 0, Serialized)
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{
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ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0)
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Local0 = \_SB.PCI0.MCHC.MHBR << 15
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Return (Local0)
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}
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/* Get EP BAR */
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Method (GEPB, 0, Serialized)
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{
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ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0)
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Local0 = \_SB.PCI0.MCHC.EPBR << 12
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Return (Local0)
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}
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/* Get PCIe BAR */
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Method (GPCB, 0, Serialized)
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{
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ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0)
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Local0 = \_SB.PCI0.MCHC.PXBR << 26
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Return (Local0)
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}
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/* Get PCIe Length */
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Method (GPCL, 0, Serialized)
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{
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ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0)
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Local0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ
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Return (Local0)
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}
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/* Get DMI BAR */
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Method (GDMB, 0, Serialized)
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{
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ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0)
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Local0 = \_SB.PCI0.MCHC.DIBR << 12
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Return (Local0)
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}
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@ -282,22 +282,22 @@ Device (PDRC)
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})
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CreateDwordField (BUF0, MCHB._BAS, MBR0)
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Store (\_SB.PCI0.GMHB (), MBR0)
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MBR0 = \_SB.PCI0.GMHB ()
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CreateDwordField (BUF0, DMIB._BAS, DBR0)
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Store (\_SB.PCI0.GDMB (), DBR0)
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DBR0 = \_SB.PCI0.GDMB ()
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CreateDwordField (BUF0, EGPB._BAS, EBR0)
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Store (\_SB.PCI0.GEPB (), EBR0)
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EBR0 = \_SB.PCI0.GEPB ()
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CreateDwordField (BUF0, PCIX._BAS, XBR0)
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Store (\_SB.PCI0.GPCB (), XBR0)
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XBR0 = \_SB.PCI0.GPCB ()
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CreateDwordField (BUF0, PCIX._LEN, XSZ0)
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Store (\_SB.PCI0.GPCL (), XSZ0)
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XSZ0 = \_SB.PCI0.GPCL ()
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CreateDwordField (BUF0, FIOH._BAS, FBR0)
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Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0)
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FBR0 = 0x100000000 - CONFIG_ROM_SIZE
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Return (BUF0)
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}
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