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soc/intel/common/block/acpi: Update northbridge.asl to ASL2.0 syntax 

This change updates northbridge.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If8eabb6b934b74e69cdf4e18981082028399244d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Furquan Shaikh 2020-05-15 18:50:09 -07:00
parent 6186cbcdc7
commit edf2c8eb55
1 changed files with 18 additions and 18 deletions
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36
src/soc/intel/common/block/acpi/acpi/northbridge.asl
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@ -183,21 +183,21 @@ Method (_CRS, 0, Serialized)
* Fix up PCI memory region * Fix up PCI memory region
* Start with Top of Lower Usable DRAM * Start with Top of Lower Usable DRAM
*/ */
Store (\_SB.PCI0.MCHC.TLUD, PMIN) PMIN = \_SB.PCI0.MCHC.TLUD
Add (Subtract (PMAX, PMIN), 1, PLEN) PLEN = PMAX - PMIN + 1
/* Patch PM02 range based on Memory Size */ /* Patch PM02 range based on Memory Size */
If (LEqual (A4GS, 0)) { If (A4GS == 0) {
CreateQwordField (MCRS, PM02._LEN, MSEN) CreateQwordField (MCRS, PM02._LEN, MSEN)
Store (0, MSEN) MSEN = 0
} Else { } Else {
CreateQwordField (MCRS, PM02._MIN, MMIN) CreateQwordField (MCRS, PM02._MIN, MMIN)
CreateQwordField (MCRS, PM02._MAX, MMAX) CreateQwordField (MCRS, PM02._MAX, MMAX)
CreateQwordField (MCRS, PM02._LEN, MLEN) CreateQwordField (MCRS, PM02._LEN, MLEN)
/* Set 64bit MMIO resource base and length */ /* Set 64bit MMIO resource base and length */
Store (A4GS, MLEN) MLEN = A4GS
Store (A4GB, MMIN) MMIN = A4GB
Subtract (Add (MMIN, MLEN), 1, MMAX) MMAX = MMIN + MLEN - 1
} }
Return (MCRS) Return (MCRS)
@ -206,35 +206,35 @@ Method (_CRS, 0, Serialized)
/* Get MCH BAR */ /* Get MCH BAR */
Method (GMHB, 0, Serialized) Method (GMHB, 0, Serialized)
{ {
ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0) Local0 = \_SB.PCI0.MCHC.MHBR << 15
Return (Local0) Return (Local0)
} }
/* Get EP BAR */ /* Get EP BAR */
Method (GEPB, 0, Serialized) Method (GEPB, 0, Serialized)
{ {
ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0) Local0 = \_SB.PCI0.MCHC.EPBR << 12
Return (Local0) Return (Local0)
} }
/* Get PCIe BAR */ /* Get PCIe BAR */
Method (GPCB, 0, Serialized) Method (GPCB, 0, Serialized)
{ {
ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0) Local0 = \_SB.PCI0.MCHC.PXBR << 26
Return (Local0) Return (Local0)
} }
/* Get PCIe Length */ /* Get PCIe Length */
Method (GPCL, 0, Serialized) Method (GPCL, 0, Serialized)
{ {
ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0) Local0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ
Return (Local0) Return (Local0)
} }
/* Get DMI BAR */ /* Get DMI BAR */
Method (GDMB, 0, Serialized) Method (GDMB, 0, Serialized)
{ {
ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0) Local0 = \_SB.PCI0.MCHC.DIBR << 12
Return (Local0) Return (Local0)
} }
@ -282,22 +282,22 @@ Device (PDRC)
}) })
CreateDwordField (BUF0, MCHB._BAS, MBR0) CreateDwordField (BUF0, MCHB._BAS, MBR0)
Store (\_SB.PCI0.GMHB (), MBR0) MBR0 = \_SB.PCI0.GMHB ()
CreateDwordField (BUF0, DMIB._BAS, DBR0) CreateDwordField (BUF0, DMIB._BAS, DBR0)
Store (\_SB.PCI0.GDMB (), DBR0) DBR0 = \_SB.PCI0.GDMB ()
CreateDwordField (BUF0, EGPB._BAS, EBR0) CreateDwordField (BUF0, EGPB._BAS, EBR0)
Store (\_SB.PCI0.GEPB (), EBR0) EBR0 = \_SB.PCI0.GEPB ()
CreateDwordField (BUF0, PCIX._BAS, XBR0) CreateDwordField (BUF0, PCIX._BAS, XBR0)
Store (\_SB.PCI0.GPCB (), XBR0) XBR0 = \_SB.PCI0.GPCB ()
CreateDwordField (BUF0, PCIX._LEN, XSZ0) CreateDwordField (BUF0, PCIX._LEN, XSZ0)
Store (\_SB.PCI0.GPCL (), XSZ0) XSZ0 = \_SB.PCI0.GPCL ()
CreateDwordField (BUF0, FIOH._BAS, FBR0) CreateDwordField (BUF0, FIOH._BAS, FBR0)
Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) FBR0 = 0x100000000 - CONFIG_ROM_SIZE
Return (BUF0) Return (BUF0)
} }