tegra124/nyan: display, clock, and other updates

tegra124: Set Tx FIFO threshold value to recommended setting
Reviewed-on: https://chromium-review.googlesource.com/175200
(cherry picked from commit c8f086711c6ae2db70fc8e0d84b54f5952fbe0ad)

tegra124: add CLK_X definitions
Reviewed-on: https://chromium-review.googlesource.com/175220
(cherry picked from commit 3f8a844bd2f151e06d82d1a7fac4492c6bc9417d)

tegra124: fix incorrect struct member in clk_rst.h
Reviewed-on: https://chromium-review.googlesource.com/175270
(cherry picked from commit 967193d5984a086c297988caa580b61cb4d0414c)

tegra124: add the _x clocks to clock_enable_clear_reset
Reviewed-on: https://chromium-review.googlesource.com/175539
(cherry picked from commit df4c515d73b02061e5c98f51efd50e04b10d63f5)

tegra124: add clock support code for graphics.
Reviewed-on: https://chromium-review.googlesource.com/175162
(cherry picked from commit b8eb6ab4cdc5a583636c10fa05f947a244f94819)

tegra124: Clean up some #defines for DMA
Reviewed-on: https://chromium-review.googlesource.com/175631
(cherry picked from commit 1a0a900f2d060916c9878781b82113b16a7945d9)

tegra124: enable flow control for APBDMA in SPI driver
Reviewed-on: https://chromium-review.googlesource.com/175630
(cherry picked from commit 873e6f9e95f6cb0162fa06216682fbc71ab0202d)

nyan: move clock setup for the display out of dca_init
Reviewed-on: https://chromium-review.googlesource.com/175656
(cherry picked from commit 32dd9947a60298ff9488c911629802c257ed6afc)

tegra124: more display PLL setup and clock hardcode removal.
Reviewed-on: https://chromium-review.googlesource.com/175732
(cherry picked from commit 80402876b5daa9e9389fd4fab5f539d89c37fa7f)

tegra124: move dp.c from tegra to tegra124
Reviewed-on: https://chromium-review.googlesource.com/175830
(cherry picked from commit e98be569b0ba7f4d565ce677343a317db08344e0)

tegra124: clean up tabbing; nyan: add a comment and setting to devicetree.cb
Reviewed-on: https://chromium-review.googlesource.com/175889
(cherry picked from commit 4e513196b0014c5a82079f3aa87c2efbeb645484)

tegra: get rid of struct members that are not used
Reviewed-on: https://chromium-review.googlesource.com/176023
(cherry picked from commit 032b8a0c9fe0152ebc27344e93128865ecb918a6)

tegra124: Increase SCLK (AVP) to 300MHz
Reviewed-on: https://chromium-review.googlesource.com/175489
(cherry picked from commit 7e082f2c2f030950d652f1f87f637e15dee38552)

tegra124: Address old main CPU starting review feedback.
Reviewed-on: https://chromium-review.googlesource.com/175933
(cherry picked from commit 1d76ac71bd839dff9198e65132ec25212dd55ffd)

tegra124: Revise clock source configuration for irregular peripherals.
Reviewed-on: https://chromium-review.googlesource.com/176109
(cherry picked from commit 1021c215190602a2b8c1ab97d6c8313d89597d99)

nyan: add timestamps in romstage
Reviewed-on: https://chromium-review.googlesource.com/176172
(cherry picked from commit cd626aa10b56cd4da6ebda36fe487e44b08f3935)

tegra124: Allow enabling clock output for external peripherals.
Reviewed-on: https://chromium-review.googlesource.com/176108
(cherry picked from commit ea9fb6393ee80da77c9fbc30f605859c7009c9ed)

nyan: Enable and configure clocks for I2S and audio codec.
Reviewed-on: https://chromium-review.googlesource.com/176104
(cherry picked from commit 1fb659b3e73285ff8218c0f229734edd3b979ca4)

tegra124: Fix typo in pinmux name.
Reviewed-on: https://chromium-review.googlesource.com/176215
(cherry picked from commit c7915ad41a3f1d1452aa6d6d287aaa8eb9e85c34)

nyan: Add pinmux settings for audio peripherals.
Reviewed-on: https://chromium-review.googlesource.com/176212
(cherry picked from commit 37412f3201590e47a06d4678fa833164d370b41c)

nyan: De-array-ify the PMIC setup code.
Reviewed-on: https://chromium-review.googlesource.com/176903
(cherry picked from commit 86ab1ce9fbf6d5362af1ee37de1394412366f247)

nyan: Add a kconfig for building for the original nyans in pixel cases.
Reviewed-on: https://chromium-review.googlesource.com/176904
(cherry picked from commit 1d05fd5bc40d727826510ec81496ce4a49e257ed)

nyan: Set the CPU voltage differently depending on which PMIC is in use.
Reviewed-on: https://chromium-review.googlesource.com/176905
(cherry picked from commit 31507f6a575220737ee5683b312cd162600f89cc)

nyan: Increase the CPU voltage to 1.2V.
Reviewed-on: https://chromium-review.googlesource.com/176906
(cherry picked from commit fe4795e66b515c2523df09a8800ecac9a3f63557)

tegra124: Flesh out/tidy up the flow controller constants.
Reviewed-on: https://chromium-review.googlesource.com/177085
(cherry picked from commit b50d315506a5ab9c81b6bbaf8cf580dbb3e78794)

tegra124: When leaving the bootblock/AVP, really stop the AVP.
Reviewed-on: https://chromium-review.googlesource.com/177086
(cherry picked from commit 06c10df889d4d935bc99792df860d93766ae44dd)

nyan: Set SPI4 speed to 33MHz
Reviewed-on: https://chromium-review.googlesource.com/177038
(cherry picked from commit c98de65482fabdb5c76944fe3bf762191b3a0a55)

nyan: Do console_init() in romstage
Reviewed-on: https://chromium-review.googlesource.com/176763
(cherry picked from commit 0bec32e09eab28bc5ea49b7896a8b6f489143b03)

nyan: Add a prompt to the CONFIG_NYAN_IN_A_PIXEL option.
Reviewed-on: https://chromium-review.googlesource.com/177486
(cherry picked from commit 7cbb801d000dac4b39f76266ebef2585fe48faba)

nyan: Separate the SDRAM BCT config for the two nyans, and turn down norrin.
Reviewed-on: https://chromium-review.googlesource.com/177487
(cherry picked from commit 6b119685f6626d79d924af9f856ebb90af45a73f)

tegra124: Bump up HCLK and PCLK
Reviewed-on: https://chromium-review.googlesource.com/177563
(cherry picked from commit c25337dac8c3ecdd8ffe5b4d11acebb216132405)

nyan: Add some code for reading the board ID.
Reviewed-on: https://chromium-review.googlesource.com/177488
(cherry picked from commit 5fccbce99e7db312e2e3caf806c438c9b04c0a8f)

nyan: Use the board ID to decide how to initialize the PMIC.
Reviewed-on: https://chromium-review.googlesource.com/177489
(cherry picked from commit 677bdb9df55248da3a0c6be0089098f6d6807d3c)

nyan: Create kconfig variables for each SDRAM config.
Reviewed-on: https://chromium-review.googlesource.com/177580
(cherry picked from commit d7ddcf262a321f06289c4f2b2a6b43982dd96377)

tegra124: Mux some unused pins away from UARTA, and pull up the serial RX line.
Reviewed-on: https://chromium-review.googlesource.com/177637
(cherry picked from commit bd533cc109b0acf3495b04fa6622e250ba454fe9)

tegra124: Initialize the MCR when setting up the UART.
Reviewed-on: https://chromium-review.googlesource.com/177638
(cherry picked from commit 38c84786fc3e8fab913aebca176ac7b038cb0be6)

tegra124: fix SPI AHB burst length
Reviewed-on: https://chromium-review.googlesource.com/177564
(cherry picked from commit f29235263202c9b4a3dbb65da5727c8eefe44315)

tegra124: remove unneeded debug print in SPI code
Reviewed-on: https://chromium-review.googlesource.com/177833
(cherry picked from commit 34a50040268dbde1c326d315f8042a3905ddfb06)

nyan: Set up the SOC and TPM reset pin.
Reviewed-on: https://chromium-review.googlesource.com/177965
(cherry picked from commit b81a5bd15a2979ee009b9f7bc4a39a304e6a759a)

tegra124: Allow some time for packets to appear in Rx FIFO
Reviewed-on: https://chromium-review.googlesource.com/177832
(cherry picked from commit 8f70a25b1eea865a448525749ac18393f5b9ad84)

nyan: PMIC: Slam default init values for SDOs/LDOs in AS3722
Reviewed-on: https://chromium-review.googlesource.com/178226
(cherry picked from commit c536b0d82fd6fffbc0e2448e0d19d3f06df5d86a)

nyan: change devicetree for the new display settings.
Reviewed-on: https://chromium-review.googlesource.com/177958
(cherry picked from commit 43abed730f222c8a685c250a58c981268994a65d)

nyan: Switch USB VBUS GPIOs from outputs to pulled-up inputs
Reviewed-on: https://chromium-review.googlesource.com/178914
(cherry picked from commit e47b6a609b9d23694a466b56960d9d14ca5d6242)

Tegra124: nyan: Disable VPR
Reviewed-on: https://chromium-review.googlesource.com/179327
(cherry picked from commit 441aa276446141f1b92ed8fb98c9578597487f4d)

tegra124: norrin: fix display issue
Reviewed-on: https://chromium-review.googlesource.com/179745
(cherry picked from commit c1c1ae69f6058ed901f532e2c532d1e6ba1f81fb)

tegra124: Add iRAM layout information.
Reviewed-on: https://chromium-review.googlesource.com/179814
(cherry picked from commit d00f135c93a52ad4dced2edecb74e2dfc54bb2fa)

tegra124: Run bootblock and ROM stage out of DRAM.
Reviewed-on: https://chromium-review.googlesource.com/179822
(cherry picked from commit 2d3ec06ec39a489d02e798bb22bce4d7465b20ce)

nyan: clean up a comment regarding video
Reviewed-on: https://chromium-review.googlesource.com/180161
(cherry picked from commit 03b5e88a66b9c96df2ef3d9ce5ba4a62a8bb2447)

tegra124: norrin: the first step to clean up display code
Reviewed-on: https://chromium-review.googlesource.com/180135
(cherry picked from commit 9d0c12dfef28a1161604df9b3fcc113049b2747d)

Squashed 49 commits for tegra124/nyan.

Change-Id: Id67bfee725e703d3e2d8ac17f40844dc193e901d
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6883
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Julius Werner 2013-10-25 17:49:26 -07:00 committed by Isaac Christensen
parent 75c83870e5
commit edf6b57f73
40 changed files with 1493 additions and 55256 deletions

View File

@ -87,4 +87,18 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 1
choice
prompt "BCT sdram configuration"
default BCT_SDRAM_792
help
The SDRAM configuration to put in the BCT.
config BCT_SDRAM_792
bool "792 MHz"
config BCT_SDRAM_924
bool "924 MHz"
endchoice
endif # BOARD_GOOGLE_NYAN

View File

@ -27,6 +27,7 @@ $(obj)/generated/bct.cfg:
subdirs-y += bct
bootblock-y += boardid.c
bootblock-y += bootblock.c
bootblock-y += pmic.c

View File

@ -20,4 +20,5 @@
bct-cfg-$(CONFIG_BCT_CFG_EMMC) += emmc.cfg
bct-cfg-$(CONFIG_BCT_CFG_SPI) += spi.cfg
bct-cfg-y += odmdata.cfg
bct-cfg-y += sdram.cfg
bct-cfg-$(CONFIG_BCT_SDRAM_924) += sdram-924.cfg
bct-cfg-$(CONFIG_BCT_SDRAM_792) += sdram-792.cfg

View File

@ -0,0 +1,346 @@
# CFG Version 07
# Do not edit. Generated by gen_sdram_cfg V4.0.7. Command:
# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.262 -dram_board_cfg 10 -fly_by_time_ps 1650
# -b PM358/PM358_792MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_792Mhz.cfg
# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.26 ns (792.39 MHz)
# bkv file: PM358/PM358_792MHz_emc_reg.txt
SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
SDRAM[0].PllMInputDivider = 0x00000001;
SDRAM[0].PllMFeedbackDivider = 0x00000042;
SDRAM[0].PllMStableTime = 0x0000012c;
SDRAM[0].PllMSetupControl = 0x00000000;
SDRAM[0].PllMSelectDiv2 = 0x00000000;
SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
SDRAM[0].PllMKCP = 0x00000000;
SDRAM[0].PllMKVCO = 0x00000000;
SDRAM[0].EmcBctSpare0 = 0x00000000;
SDRAM[0].EmcBctSpare1 = 0x00000000;
SDRAM[0].EmcBctSpare2 = 0x00000000;
SDRAM[0].EmcBctSpare3 = 0x00000000;
SDRAM[0].EmcBctSpare4 = 0x00000000;
SDRAM[0].EmcBctSpare5 = 0x00000000;
SDRAM[0].EmcBctSpare6 = 0x00000000;
SDRAM[0].EmcBctSpare7 = 0x00000000;
SDRAM[0].EmcBctSpare8 = 0x00000000;
SDRAM[0].EmcBctSpare9 = 0x00000000;
SDRAM[0].EmcBctSpare10 = 0x00000000;
SDRAM[0].EmcBctSpare11 = 0x00000000;
SDRAM[0].EmcClockSource = 0x80000000;
SDRAM[0].EmcAutoCalInterval = 0x001fffff;
SDRAM[0].EmcAutoCalConfig = 0xa1430000;
SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
SDRAM[0].EmcAutoCalWait = 0x00000190;
SDRAM[0].EmcAdrCfg = 0x00000000;
SDRAM[0].EmcPinProgramWait = 0x00000001;
SDRAM[0].EmcPinExtraWait = 0x00000000;
SDRAM[0].EmcTimingControlWait = 0x00000000;
SDRAM[0].EmcRc = 0x00000025;
SDRAM[0].EmcRfc = 0x000000cd;
SDRAM[0].EmcRfcSlr = 0x00000000;
SDRAM[0].EmcRas = 0x00000019;
SDRAM[0].EmcRp = 0x0000000a;
SDRAM[0].EmcR2r = 0x00000000;
SDRAM[0].EmcW2w = 0x00000000;
SDRAM[0].EmcR2w = 0x00000007;
SDRAM[0].EmcW2r = 0x0000000d;
SDRAM[0].EmcR2p = 0x00000004;
SDRAM[0].EmcW2p = 0x00000013;
SDRAM[0].EmcRdRcd = 0x0000000a;
SDRAM[0].EmcWrRcd = 0x0000000a;
SDRAM[0].EmcRrd = 0x00000003;
SDRAM[0].EmcRext = 0x00000002;
SDRAM[0].EmcWext = 0x00000000;
SDRAM[0].EmcWdv = 0x00000006;
SDRAM[0].EmcWdvMask = 0x00000006;
SDRAM[0].EmcQUse = 0x0000000b;
SDRAM[0].EmcQuseWidth = 0x00000002;
SDRAM[0].EmcIbdly = 0x00000000;
SDRAM[0].EmcEInput = 0x00000003;
SDRAM[0].EmcEInputDuration = 0x0000000c;
SDRAM[0].EmcPutermExtra = 0x00090000;
SDRAM[0].EmcPutermWidth = 0x00000004;
SDRAM[0].EmcPutermAdj = 0x00000000;
SDRAM[0].EmcCdbCntl1 = 0x00000000;
SDRAM[0].EmcCdbCntl2 = 0x00000000;
SDRAM[0].EmcCdbCntl3 = 0x00000000;
SDRAM[0].EmcQRst = 0x00000002;
SDRAM[0].EmcQSafe = 0x00000011;
SDRAM[0].EmcRdv = 0x00000017;
SDRAM[0].EmcRdvMask = 0x00000019;
SDRAM[0].EmcQpop = 0x0000000f;
SDRAM[0].EmcCtt = 0x00000000;
SDRAM[0].EmcCttDuration = 0x00000004;
SDRAM[0].EmcRefresh = 0x000017eb;
SDRAM[0].EmcBurstRefreshNum = 0x00000000;
SDRAM[0].EmcPreRefreshReqCnt = 0x000005fa;
SDRAM[0].EmcPdEx2Wr = 0x00000003;
SDRAM[0].EmcPdEx2Rd = 0x00000003;
SDRAM[0].EmcPChg2Pden = 0x00000001;
SDRAM[0].EmcAct2Pden = 0x00000000;
SDRAM[0].EmcAr2Pden = 0x000000c7;
SDRAM[0].EmcRw2Pden = 0x00000018;
SDRAM[0].EmcTxsr = 0x000000d7;
SDRAM[0].EmcTxsrDll = 0x00000200;
SDRAM[0].EmcTcke = 0x00000005;
SDRAM[0].EmcTckesr = 0x00000006;
SDRAM[0].EmcTpd = 0x00000005;
SDRAM[0].EmcTfaw = 0x0000001d;
SDRAM[0].EmcTrpab = 0x00000000;
SDRAM[0].EmcTClkStable = 0x00000008;
SDRAM[0].EmcTClkStop = 0x00000008;
SDRAM[0].EmcTRefBw = 0x0000182c;
SDRAM[0].EmcFbioCfg5 = 0x104ab898;
SDRAM[0].EmcFbioCfg6 = 0x00000002;
SDRAM[0].EmcFbioSpare = 0x00000000;
SDRAM[0].EmcCfgRsv = 0xff00ff00;
SDRAM[0].EmcMrs = 0x80001d71;
SDRAM[0].EmcEmrs = 0x80100002;
SDRAM[0].EmcEmrs2 = 0x80200018;
SDRAM[0].EmcEmrs3 = 0x80300000;
SDRAM[0].EmcMrw1 = 0x00000000;
SDRAM[0].EmcMrw2 = 0x00000000;
SDRAM[0].EmcMrw3 = 0x00000000;
SDRAM[0].EmcMrw4 = 0x00000000;
SDRAM[0].EmcMrwExtra = 0x00000000;
SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
SDRAM[0].EmcMrwResetCommand = 0x00000000;
SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
SDRAM[0].EmcMrsWaitCnt = 0x00f7000e;
SDRAM[0].EmcMrsWaitCnt2 = 0x00f7000e;
SDRAM[0].EmcCfg = 0x73300000;
SDRAM[0].EmcCfg2 = 0x0000089d;
SDRAM[0].EmcCfgPipe = 0x000040a0;
SDRAM[0].EmcDbg = 0x01000c00;
SDRAM[0].EmcCmdQ = 0x10004408;
SDRAM[0].EmcMc2EmcQ = 0x06000404;
SDRAM[0].EmcDynSelfRefControl = 0x80003025;
SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
SDRAM[0].EmcCfgDigDll = 0xe00701b1;
SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
SDRAM[0].EmcDevSelect = 0x00000002;
SDRAM[0].EmcSelDpdCtrl = 0x00040000;
SDRAM[0].EmcDllXformDqs0 = 0x00000008;
SDRAM[0].EmcDllXformDqs1 = 0x00000008;
SDRAM[0].EmcDllXformDqs2 = 0x00000008;
SDRAM[0].EmcDllXformDqs3 = 0x00000008;
SDRAM[0].EmcDllXformDqs4 = 0x00000008;
SDRAM[0].EmcDllXformDqs5 = 0x00000008;
SDRAM[0].EmcDllXformDqs6 = 0x00000008;
SDRAM[0].EmcDllXformDqs7 = 0x00000008;
SDRAM[0].EmcDllXformDqs8 = 0x00000008;
SDRAM[0].EmcDllXformDqs9 = 0x00000008;
SDRAM[0].EmcDllXformDqs10 = 0x00000008;
SDRAM[0].EmcDllXformDqs11 = 0x00000008;
SDRAM[0].EmcDllXformDqs12 = 0x00000008;
SDRAM[0].EmcDllXformDqs13 = 0x00000008;
SDRAM[0].EmcDllXformDqs14 = 0x00000008;
SDRAM[0].EmcDllXformDqs15 = 0x00000008;
SDRAM[0].EmcDllXformQUse0 = 0x00000000;
SDRAM[0].EmcDllXformQUse1 = 0x00000000;
SDRAM[0].EmcDllXformQUse2 = 0x00000000;
SDRAM[0].EmcDllXformQUse3 = 0x00000000;
SDRAM[0].EmcDllXformQUse4 = 0x00000000;
SDRAM[0].EmcDllXformQUse5 = 0x00000000;
SDRAM[0].EmcDllXformQUse6 = 0x00000000;
SDRAM[0].EmcDllXformQUse7 = 0x00000000;
SDRAM[0].EmcDllXformAddr0 = 0x0000000e;
SDRAM[0].EmcDllXformAddr1 = 0x0000000e;
SDRAM[0].EmcDllXformAddr2 = 0x00000000;
SDRAM[0].EmcDllXformAddr3 = 0x0000000e;
SDRAM[0].EmcDllXformAddr4 = 0x00000000;
SDRAM[0].EmcDllXformAddr5 = 0x00000000;
SDRAM[0].EmcDllXformQUse8 = 0x00000000;
SDRAM[0].EmcDllXformQUse9 = 0x00000000;
SDRAM[0].EmcDllXformQUse10 = 0x00000000;
SDRAM[0].EmcDllXformQUse11 = 0x00000000;
SDRAM[0].EmcDllXformQUse12 = 0x00000000;
SDRAM[0].EmcDllXformQUse13 = 0x00000000;
SDRAM[0].EmcDllXformQUse14 = 0x00000000;
SDRAM[0].EmcDllXformQUse15 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000;
SDRAM[0].EmcDllXformDq0 = 0x0000000b;
SDRAM[0].EmcDllXformDq1 = 0x0000000b;
SDRAM[0].EmcDllXformDq2 = 0x0000000b;
SDRAM[0].EmcDllXformDq3 = 0x0000000b;
SDRAM[0].EmcDllXformDq4 = 0x0000000b;
SDRAM[0].EmcDllXformDq5 = 0x0000000b;
SDRAM[0].EmcDllXformDq6 = 0x0000000b;
SDRAM[0].EmcDllXformDq7 = 0x0000000b;
SDRAM[0].WarmBootWait = 0x00000002;
SDRAM[0].EmcCttTermCtrl = 0x00000802;
SDRAM[0].EmcOdtWrite = 0x00000000;
SDRAM[0].EmcOdtRead = 0x00000000;
SDRAM[0].EmcZcalInterval = 0x00020000;
SDRAM[0].EmcZcalWaitCnt = 0x00000042;
SDRAM[0].EmcZcalMrwCmd = 0x80000000;
SDRAM[0].EmcMrsResetDll = 0x00000000;
SDRAM[0].EmcZcalInitDev0 = 0x80000011;
SDRAM[0].EmcZcalInitDev1 = 0x00000000;
SDRAM[0].EmcZcalInitWait = 0x00000001;
SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
SDRAM[0].EmcMrsResetDllWait = 0x00000000;
SDRAM[0].EmcMrsExtra = 0x80001d71;
SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
SDRAM[0].EmcDdr2Wait = 0x00000000;
SDRAM[0].EmcClkenOverride = 0x00000000;
SDRAM[0].McDisExtraSnapLevels = 0x00000000;
SDRAM[0].EmcExtraRefreshNum = 0x00000002;
SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
SDRAM[0].PmcVddpSel = 0x00000002;
SDRAM[0].PmcVddpSelWait = 0x00000002;
SDRAM[0].PmcDdrPwr = 0x00000003;
SDRAM[0].PmcDdrCfg = 0x00002002;
SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
SDRAM[0].PmcRegShort = 0x00000000;
SDRAM[0].PmcNoIoPower = 0x00000000;
SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0;
SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d;
SDRAM[0].EmcXm2DqsPadCtrl3 = 0x61861820;
SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514;
SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514;
SDRAM[0].EmcXm2DqsPadCtrl6 = 0x61861800;
SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085;
SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000707;
SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000;
SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x017fffff;
SDRAM[0].EmcAcpdControl = 0x00000000;
SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
SDRAM[0].EmcDsrVttgenDrv = 0x0505003f;
SDRAM[0].EmcTxdsrvttgen = 0x00000000;
SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
SDRAM[0].McEmemAdrCfg = 0x00000000;
SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
SDRAM[0].McEmemCfg = 0x00000800;
SDRAM[0].McEmemArbCfg = 0x0e00000b;
SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
SDRAM[0].McEmemArbTimingRcd = 0x00000004;
SDRAM[0].McEmemArbTimingRp = 0x00000005;
SDRAM[0].McEmemArbTimingRc = 0x00000013;
SDRAM[0].McEmemArbTimingRas = 0x0000000c;
SDRAM[0].McEmemArbTimingFaw = 0x0000000f;
SDRAM[0].McEmemArbTimingRrd = 0x00000002;
SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003;
SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c;
SDRAM[0].McEmemArbTimingR2R = 0x00000002;
SDRAM[0].McEmemArbTimingW2W = 0x00000002;
SDRAM[0].McEmemArbTimingR2W = 0x00000005;
SDRAM[0].McEmemArbTimingW2R = 0x00000008;
SDRAM[0].McEmemArbDaTurns = 0x08050202;
SDRAM[0].McEmemArbDaCovers = 0x00170e13;
SDRAM[0].McEmemArbMisc0 = 0x736c2414;
SDRAM[0].McEmemArbMisc1 = 0x70000f02;
SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
SDRAM[0].McEmemArbOverride = 0x10000000;
SDRAM[0].McEmemArbOverride1 = 0x00000000;
SDRAM[0].McEmemArbRsv = 0xff00ff00;
SDRAM[0].McClkenOverride = 0x00000000;
SDRAM[0].McStatControl = 0x00000000;
SDRAM[0].McDisplaySnapRing = 0x00000003;
SDRAM[0].McVideoProtectBom = 0xfff00000;
SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
SDRAM[0].McVideoProtectSizeMb = 0x00000000;
SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
SDRAM[0].McSecCarveoutBom = 0xfff00000;
SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
SDRAM[0].EmcCaTrainingEnable = 0x00000000;
SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
SDRAM[0].BootRomPatchControl = 0x00000000;
SDRAM[0].BootRomPatchData = 0x00000000;
SDRAM[0].McMtsCarveoutBom = 0xfff00000;
SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000013;
#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000017c;
#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00810038;
#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00810038;
#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x0081003c;
#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00810090;
#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00810041;
#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00810090;
#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00810041;
#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00810080;
#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00810004;
#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00810004;
#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x00000081;
#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00810004;
#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00810019;
#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00810018;
#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00810024;
#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x0081001c;
#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x00000081;
#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00810081;
#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00810081;
#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00810081;
#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00810081;
#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00810065;
#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x0081001c;

View File

@ -0,0 +1,38 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <soc/nvidia/tegra124/gpio.h>
#include "boardid.h"
uint8_t board_id(void)
{
static int id = -1;
if (id < 0) {
id = gpio_get_in_value(GPIO(Q3)) << 0 |
gpio_get_in_value(GPIO(T1)) << 1 |
gpio_get_in_value(GPIO(X1)) << 2 |
gpio_get_in_value(GPIO(X4)) << 3;
printk(BIOS_SPEW, "Board ID: %#x.\n", id);
}
return id;
}

View File

@ -17,13 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __SOC_NVIDIA_TEGRA124_CPUG_H__
#define __SOC_NVIDIA_TEGRA124_CPUG_H__
#ifndef __MAINBOARD_GOOGLE_NYAN_BOARDID_H__
#define __MAINBOARD_GOOGLE_NYAN_BOARDID_H__
#include <stdint.h>
extern u32 cpug_stack_pointer;
extern u32 cpug_entry_point;
void cpug_setup(void);
uint8_t board_id(void);
#endif /* __SOC_NVIDIA_TEGRA124_CPUG_H__ */
#endif /* __MAINBOARD_GOOGLE_NYAN_BOARDID_H__ */

View File

@ -25,6 +25,7 @@
#include <soc/clock.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/clk_rst.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <soc/nvidia/tegra124/pinmux.h>
#include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */
@ -41,6 +42,10 @@ static void set_clock_sources(void)
/* TODO: is the 1.333MHz correct? This may have always been bogus... */
clock_configure_source(i2c5, CLK_M, 1333);
/* TODO: We should be able to set this to 50MHz, but that did not seem
* reliable. */
clock_configure_source(sbc4, PLLP, 33333);
}
void bootblock_mainboard_init(void)
@ -49,7 +54,13 @@ void bootblock_mainboard_init(void)
clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
CLK_H_I2C5 | CLK_H_APBDMA,
0, CLK_V_MSELECT, 0);
0, CLK_V_MSELECT, 0, 0);
// Board ID GPIOs, bits 0-3.
gpio_input(GPIO(Q3));
gpio_input(GPIO(T1));
gpio_input(GPIO(X1));
gpio_input(GPIO(X4));
// I2C5 (PMU) clock.
pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,

View File

@ -26,9 +26,11 @@ chip soc/nvidia/tegra124
# are no single-access resources such as the infamous
# cf8/cfc registers found on PCs.
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "2560"
register "yres" = "1700"
register "framebuffer_bits_per_pixel" = "24"
register "xres" = "1366"
register "yres" = "768"
# this setting is what nvidia does; it makes no sense
# and does not agree with hardware. Why'd they do it?
register "framebuffer_bits_per_pixel" = "18"
register "cache_policy" = "DCACHE_WRITETHROUGH"
# With some help from the mainbaord designer
@ -57,14 +59,22 @@ chip soc/nvidia/tegra124
#V sync = 1713 - 1703 = 10
#V back porch = 1749 - 1713 = 36
#href_to_sync and vref_to_sync are from the vendor
register "href_to_sync" = "11"
register "hfront_porch" = "48"
register "hsync_width" = "32"
register "hback_porch" = "80"
#this is just an example for a Pixel panel; other panels differ.
# Here is a peppy panel:
# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
# h: width 1366 start 1502 end 1532 total 1592
# v: height 768 start 776 end 788 total 800
# These numbers were provided by Nvidia.
register "href_to_sync" = "1"
register "hfront_porch" = "44"
register "hsync_width" = "46"
register "hback_porch" = "44"
register "vref_to_sync" = "1"
register "vfront_porch" = "3"
register "vsync_width" = "10"
register "vback_porch" = "36"
register "vfront_porch" = "6"
register "vsync_width" = "8"
register "vback_porch" = "6"
# we *know* the pixel clock for this system.
register "pixel_clock" = "71"
end

View File

@ -25,6 +25,7 @@
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/clk_rst.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <soc/nvidia/tegra124/mc.h>
#include <soc/nvidia/tegra124/pmc.h>
#include <soc/nvidia/tegra124/spi.h>
#include <soc/nvidia/tegra124/usb.h>
@ -48,15 +49,24 @@ static void set_clock_sources(void)
clock_configure_source(sdmmc3, PLLP, 48000);
clock_configure_source(sdmmc4, PLLP, 48000);
/* PLLP and PLLM are switched for HOST1x for no apparent reason. */
write32(4 /* PLLP! */ << CLK_SOURCE_SHIFT |
/* TODO(rminnich): The divisor isn't accurate enough to get to
* 144MHz (it goes to 163 instead). What should we do here? */
CLK_DIVIDER(TEGRA_PLLP_KHZ, 144000),
&clk_rst->clk_src_host1x);
/* External peripheral 1: audio codec (max98090) using 12MHz CLK1.
* Note the source id of CLK_M for EXTPERIPH1 is 3. */
clock_configure_irregular_source(extperiph1, CLK_M, 12000, 3);
/*
* I2S1 can use either PLLP or PLLA. Using PLLP is sufficient now since
* we only need 4.8MHz. Note the source id of PLLP for I2S is 4.
*/
clock_configure_irregular_source(i2s1, PLLP, 4800, 4);
/* Note source id of PLLP for HOST1x is 4. */
clock_configure_irregular_source(host1x, PLLP, 408000, 4);
/* Use PLLD_OUT0 as clock source for disp1 */
clrsetbits_le32(&clk_rst->clk_src_disp1,
CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
/* DISP1 doesn't support a divisor. Use PLLC which runs at 600MHz. */
clock_configure_source(disp1, PLLC, 600000);
}
static void setup_pinmux(void)
@ -74,6 +84,9 @@ static void setup_pinmux(void)
// EC in RW.
gpio_input_pullup(GPIO(U4));
// SOC and TPM reset GPIO, active low.
gpio_output(GPIO(I5), 1);
// SPI1 MOSI
pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
PINMUX_PULL_UP |
@ -169,10 +182,25 @@ static void setup_pinmux(void)
pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX,
PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up);
/* TODO: This is supposed to work with the USB special function pinmux,
* but it doesn't. Go with GPIOs for now and solve the problem later. */
gpio_output_open_drain(GPIO(N4), 1); /* USB VBUS EN0 */
gpio_output_open_drain(GPIO(N5), 1); /* USB VBUS EN1 */
/* We pull the USB VBUS signals up but keep them as inputs since the
* voltage source likes to drive them low on overcurrent conditions */
gpio_input_pullup(GPIO(N4)); /* USB VBUS EN0 */
gpio_input_pullup(GPIO(N5)); /* USB VBUS EN1 */
/* Clock output 1 (for external peripheral) */
pinmux_set_config(PINMUX_DAP_MCLK1_INDEX,
PINMUX_DAP_MCLK1_FUNC_EXTPERIPH1 | PINMUX_PULL_NONE);
/* I2S1 */
pinmux_set_config(PINMUX_DAP2_DIN_INDEX,
PINMUX_DAP2_DIN_FUNC_I2S1 | PINMUX_TRISTATE |
PINMUX_INPUT_ENABLE);
pinmux_set_config(PINMUX_DAP2_DOUT_INDEX,
PINMUX_DAP2_DOUT_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
pinmux_set_config(PINMUX_DAP2_FS_INDEX,
PINMUX_DAP2_FS_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
pinmux_set_config(PINMUX_DAP2_SCLK_INDEX,
PINMUX_DAP2_SCLK_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
}
static void setup_kernel_info(void)
@ -185,6 +213,12 @@ static void setup_kernel_info(void)
// value defined in BCT.
struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
writel(0x80080000, &pmc->odmdata);
// Not strictly info, but kernel graphics driver needs this region locked down
struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
writel(0, &mc->mc_vpr_bom);
writel(0, &mc->mc_vpr_size);
writel(1, &mc->mc_vpr_ctrl);
}
static void setup_ec_spi(void)
@ -201,13 +235,35 @@ static void setup_ec_spi(void)
static void mainboard_init(device_t dev)
{
set_clock_sources();
clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 |
CLK_L_SDMMC4 | CLK_L_USBD,
clock_external_output(1); /* For external MAX98090 audio codec. */
/*
* Confirmed by NVIDIA hardware team, we need to take ALL audio devices
* conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
* of reset and clock-enabled, otherwise reading AHUB devices (In our
* case, I2S/APBIF/AUDIO<XBAR>) will hang.
*/
clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
CLK_L_HOST1X,
CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 |
CLK_H_PMC | CLK_H_MEM | CLK_H_USB3,
CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3,
CLK_V_I2C4,
CLK_W_DVFS);
CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF |
CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 |
CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2,
CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0,
CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 |
CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 |
CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
CLK_X_AFC5);
usb_setup_utmip1();
/* USB2 is the camera, we don't need it in firmware */

View File

@ -23,36 +23,76 @@
#include <stdint.h>
#include <stdlib.h>
#include "boardid.h"
#include "pmic.h"
struct pmic_write
{
uint8_t reg; // Register to write.
uint8_t val; // Value to write.
};
enum {
AS3722_I2C_ADDR = 0x40
};
static struct pmic_write pmic_writes[] =
struct as3722_init_reg {
u8 reg;
u8 val;
};
static struct as3722_init_reg init_list[] = {
{AS3722_SDO0, 0x3C},
{AS3722_SDO1, 0x32},
{AS3722_SDO2, 0x3C},
{AS3722_SDO3, 0x00},
{AS3722_SDO4, 0x00},
{AS3722_SDO5, 0x50},
{AS3722_SDO6, 0x28},
{AS3722_LDO0, 0x8A},
{AS3722_LDO1, 0x00},
{AS3722_LDO2, 0x10},
{AS3722_LDO3, 0x59},
{AS3722_LDO4, 0x00},
{AS3722_LDO5, 0x00},
{AS3722_LDO6, 0x3F},
{AS3722_LDO7, 0x00},
{AS3722_LDO9, 0x00},
{AS3722_LDO10, 0x00},
{AS3722_LDO11, 0x00},
};
#define AS3722_INIT_REG_LEN ARRAY_SIZE(init_list)
static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val)
{
/* Don't need to set up VDD_CORE - already done - by OTP */
i2c_write(bus, AS3722_I2C_ADDR, reg, 1, &val, 1);
udelay(10 * 1000);
}
/* First set VDD_CPU to 1.0V, then enable the VDD_CPU regulator. */
{ 0x00, 0x28 },
static void pmic_slam_defaults(unsigned bus)
{
int i;
/* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */
for (i = 0; i < AS3722_INIT_REG_LEN; i++)
pmic_write_reg(bus, init_list[i].reg, init_list[i].val);
}
void pmic_init(unsigned bus)
{
/*
* Don't need to set up VDD_CORE - already done - by OTP
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
*/
/* Restore PMIC POR defaults, in case kernel changed 'em */
pmic_slam_defaults(bus);
/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
if (board_id() == 0)
pmic_write_reg(bus, 0x00, 0x3c);
else
pmic_write_reg(bus, 0x00, 0x50);
/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
{ 0x06, 0x28 },
/* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */
pmic_write_reg(bus, 0x06, 0x28);
/* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */
{ 0x12, 0x10 },
/* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
pmic_write_reg(bus, 0x12, 0x10);
/*
* Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
@ -61,23 +101,12 @@ static struct pmic_write pmic_writes[] =
* NOTE: We do this early because doing it later seems to hose the CPU
* power rail/partition startup. Need to debug.
*/
{ 0x16, 0x3f },
pmic_write_reg(bus, 0x16, 0x3f);
/* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
/* panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
/*
* Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
* the value (register 0x20 bit 4)
*/
{ 0x0c, 0x07 },
{ 0x20, 0x10 },
};
void pmic_init(unsigned bus)
{
int i;
for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) {
i2c_write(bus, AS3722_I2C_ADDR, pmic_writes[i].reg, 1,
&pmic_writes[i].val, 1);
udelay(10 * 1000);
}
pmic_write_reg(bus, 0x0c, 0x07);
pmic_write_reg(bus, 0x20, 0x10);
}

View File

@ -20,6 +20,29 @@
#ifndef __MAINBOARD_GOOGLE_NYAN_PMIC_H__
#define __MAINBOARD_GOOGLE_NYAN_PMIC_H__
enum {
AS3722_SDO0 = 0,
AS3722_SDO1,
AS3722_SDO2,
AS3722_SDO3,
AS3722_SDO4,
AS3722_SDO5,
AS3722_SDO6,
AS3722_LDO0 = 0x10,
AS3722_LDO1,
AS3722_LDO2,
AS3722_LDO3,
AS3722_LDO4,
AS3722_LDO5,
AS3722_LDO6,
AS3722_LDO7,
AS3722_LDO9 = 0x19,
AS3722_LDO10,
AS3722_LDO11,
};
void pmic_init(unsigned bus);
#endif /* __MAINBOARD_GOOGLE_NYAN_PMIC_H__ */

View File

@ -27,6 +27,7 @@
#include <console/console.h>
#include "soc/nvidia/tegra124/chip.h"
#include <soc/display.h>
#include <timestamp.h>
// Convenient shorthand (in MB)
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
@ -73,6 +74,10 @@ static void configure_l2actlr(void)
void main(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t romstage_start_time = timestamp_get();
#endif
// Globally disable MMU, caches and branch prediction (these should
// already be disabled by default on reset).
uint32_t sctlr = read_sctlr();
@ -89,6 +94,8 @@ void main(void)
configure_l2ctlr();
configure_l2actlr();
console_init();
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
@ -101,12 +108,15 @@ void main(void)
exception_init();
/* for quality of the user interface, it's important to get
/* For quality of the user experience, it's important to get
* the video going ASAP. Because there are long delays in some
* of the powerup steps, we do some very early setup here in
* romstage. We don't do this in the bootblock because video
* setup is finicky and subject to change; hence, we do it as
* early as we can in the RW stage, but never in the RO stage.
* romstage. The only thing setup_display does is manage
* 4 GPIOs, under control of the config struct members.
* In general, it is safe to enable panel power, and disable
* anything related to the backlight. If we get something wrong,
* we can easily fix it in ramstage by further GPIO manipulation,
* so we feel it is ok to do some setting at this point.
*/
const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0);
@ -119,7 +129,15 @@ void main(void)
cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(0);
timestamp_add(TS_START_ROMSTAGE, romstage_start_time);
timestamp_add(TS_START_COPYRAM, timestamp_get());
#endif
void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
"fallback/coreboot_ram");
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_add(TS_END_COPYRAM, timestamp_get());
#endif
stage_exit(entry);
}

View File

@ -171,10 +171,8 @@ enum {
#define EDP_PWR_OFF_TO_ON_TIME_MS (500+10)
struct tegra_dc_dp_data {
struct tegra_dc *dc;
struct tegra_dc_sor_data *sor;
struct tegra_dc_sor_data sor;
void *aux_base;
struct tegra_dc_mode *mode;
struct tegra_dc_dp_link_config link_cfg;
};

View File

@ -93,13 +93,13 @@ void usb_setup_utmip(struct usb_ctlr *usb)
}
/*
* Tegra EHCI controllers need their usb_mode and lpm_ctrl registers initialized
* after every EHCI reset and before any other actions (such as Run/Stop bit)
* are taken. We reset the controller here, set those registers and rely on the
* fact that libpayload doesn't reset EHCI controllers on initialization for
* whatever weird reason. This is ugly, fragile, and I really don't like it, but
* making this work will require an ugly hack one way or another so we might as
* well take the path of least resistance for now.
* Tegra EHCI controllers need their usb_mode, lpm_ctrl and tx_fill_tuning
* registers initialized after every EHCI reset and before any other actions
* (such as Run/Stop bit) are taken. We reset the controller here, set those
* registers and rely on the fact that libpayload doesn't reset EHCI controllers
* on initialization for whatever weird reason. This is ugly, fragile, and I
* really don't like it, but making this work will require an ugly hack one way
* or another so we might as well take the path of least resistance for now.
*/
void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type)
{
@ -117,4 +117,5 @@ void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type)
write32(3 << 0, &usb->usb_mode); /* Controller mode: HOST */
write32(type << 29, &usb->lpm_ctrl); /* Parallel transceiver selct */
write32(0x10 << 16, &usb->tx_fill_tuning); /* Tx FIFO Burst thresh */
}

View File

@ -24,6 +24,20 @@ config BOOTBLOCK_CPU_INIT
# 0x00000 Combined bootblock and BCT blob
# 0x18000 Master CBFS header.
# 0x18080 Free for CBFS data.
#
# iRAM (256k) layout.
# 0x4000_0000 BootROM runtime data/stack area, can be reclaimed after BootROM.
# +0000 (BootROM) Boot Information Table.
# +0100 (BootROM) BCT.
# ---------------------------------------------------------------------
# +0000 (Coreboot) TTB 16KB.
# +4000 (Coreboot) Stack.
# 0x4000_E000 Valid for anything to be executed after BootROM (effective entry
# point address specified in BCT).
# +0000 (Coreboot) Bootblock (max 36k).
# +9000 (Coreboot) ROM stage (max 36k).
# 0x4002_0000 (Coreboot) Cache of CBFS.
# 0x4003_FFFF End of iRAM.
config BOOTBLOCK_ROM_OFFSET
hex
@ -43,11 +57,11 @@ config SYS_SDRAM_BASE
config BOOTBLOCK_BASE
hex
default 0x80000000
default 0x4000e000
config ROMSTAGE_BASE
hex
default 0x80100000
default 0x40017000
config RAMSTAGE_BASE
hex
@ -55,11 +69,11 @@ config RAMSTAGE_BASE
config STACK_TOP
hex
default 0x80400000
default 0x4000c000
config STACK_BOTTOM
hex
default 0x803f8000
default 0x40004000
config STACK_SIZE
hex
@ -72,7 +86,7 @@ config TTB_BUFFER
config CBFS_CACHE_ADDRESS
hex "memory address to put CBFS cache data"
default 0x803c0000
default 0x40020000
config CBFS_CACHE_SIZE
hex "size of CBFS cache data"

View File

@ -2,10 +2,10 @@ bootblock-y += bootblock.c
bootblock-y += bootblock_asm.S
bootblock-y += cbfs.c
bootblock-y += clock.c
bootblock-y += cpug.S
bootblock-y += dma.c
bootblock-y += i2c.c
bootblock-y += dma.c
bootblock-y += maincpu.S
bootblock-y += monotonic_timer.c
bootblock-y += power.c
bootblock-y += spi.c
@ -33,16 +33,16 @@ romstage-$(CONFIG_CONSOLE_SERIAL) += uart.c
ramstage-y += cbfs.c
ramstage-y += cbmem.c
ramstage-y += cpug.S
ramstage-y += clock.c
ramstage-y += display.c displayhack.c
ramstage-y += dma.c
ramstage-y += i2c.c
ramstage-y += maincpu.S
ramstage-y += monotonic_timer.c
ramstage-y += soc.c
ramstage-y += sor.c
ramstage-y += spi.c
ramstage-y += ../tegra/dp.c
ramstage-y += dp.c
ramstage-y += ../tegra/gpio.c
ramstage-y += ../tegra/i2c.c
ramstage-y += ../tegra/pinmux.c

View File

@ -37,7 +37,15 @@ void main(void)
// Serial in, tristate_on.
pinmux_set_config(PINMUX_KB_ROW10_INDEX, PINMUX_KB_ROW10_FUNC_UA3 |
PINMUX_TRISTATE |
PINMUX_PULL_UP |
PINMUX_INPUT_ENABLE);
// Mux some pins away from uart A.
pinmux_set_config(PINMUX_UART2_CTS_N_INDEX,
PINMUX_UART2_CTS_N_FUNC_UB3 |
PINMUX_TRISTATE |
PINMUX_INPUT_ENABLE);
pinmux_set_config(PINMUX_UART2_RTS_N_INDEX,
PINMUX_UART2_RTS_N_FUNC_UB3);
if (CONFIG_BOOTBLOCK_CONSOLE)
console_init();
@ -63,5 +71,5 @@ void main(void)
if (entry)
clock_cpu0_config_and_reset(entry);
hlt();
clock_halt_avp();
}

View File

@ -269,11 +269,13 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr {
u32 _rsv31; /* 0x554 */
u32 super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER, 0x558 */
u32 spare_reg0; /* _SPARE_REG0, 0x55c */
u32 _rsv32[11]; /* 0x560-58c */
u32 _rsv32[4]; /* 0x560-0x56c */
u32 plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */
u32 _rsv32_1[7]; /* 0x574-58c */
u32 plldp_base; /* _PLLDP_BASE, 0x590 */
u32 plldp_misc; /* _PLLDP_MISC, 0x594 */
u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
u32 _rsrv321[26];
u32 _rsrv32_2[25];
u32 clk_src_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST 0x600 */
u32 clk_src_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON 0x604 */
u32 clk_src_xusb_fs; /* _CLK_SOURCE_XUSB_FS 0x608 */
@ -360,17 +362,15 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr {
/* CLK_RST_CONTROLLER_PLL*_OUT*_0 */
#define PLL_OUT_RSTN (1 << 0)
#define PLL_OUT_CLKEN (1 << 1)
#define PLL_OUT_OVRRIDE (1 << 2)
#define PLL_OUT_OVR (1 << 2)
#define PLL_OUT_RATIO_SHIFT 8
#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
#define PLL_OUT2_RSTN (1 << 16)
#define PLL_OUT2_CLKEN (1 << 17)
#define PLL_OUT2_OVRRIDE (1 << 18)
#define PLL_OUT2_RATIO_SHIFT 24
#define PLL_OUT2_RATIO_MASK (0xffU << PLL_OUT2_RATIO_SHIFT)
#define PLL_OUT1_SHIFT 0
#define PLL_OUT2_SHIFT 16
#define PLL_OUT3_SHIFT 0
#define PLL_OUT4_SHIFT 16
/* CLK_RST_CONTROLLER_PLL*_MISC_0 */
#define PLL_MISC_DCCON (1 << 20)
@ -382,38 +382,15 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr {
#define PLL_MISC_LFCON_MASK (0xfU << PLL_MISC_LFCON_SHIFT)
/* This bit is different all over the place. Oh joy... */
#define PLLDPD2_MISC_LOCK_ENABLE (1 << 30)
#define PLLC_MISC_LOCK_ENABLE (1 << 24)
#define PLLUD_MISC_LOCK_ENABLE (1 << 22)
#define PLLD_MISC_CLK_ENABLE (1 << 30)
#define PLLPAXS_MISC_LOCK_ENABLE (1 << 18)
#define PLLE_MISC_LOCK_ENABLE (1 << 9)
#define PLLU_MISC_VCO_FREQ (1 << 20)
#define PLLP_OUT1_OVR (1 << 2)
#define PLLP_OUT2_OVR (1 << 18)
#define PLLP_OUT3_OVR (1 << 2)
#define PLLP_OUT4_OVR (1 << 18)
#define PLLP_OUT1_RATIO 8
#define PLLP_OUT2_RATIO 24
#define PLLP_OUT3_RATIO 8
#define PLLP_OUT4_RATIO 24
#define PLLP_OUT3_RSTN_DIS (1 << 0)
#define PLLP_OUT3_RSTN_EN (0 << 0)
#define PLLP_OUT3_CLKEN (1 << 1)
#define PLLP_OUT3_OVRRIDE (1 << 2)
#define PLLP_OUT4_RSTN_DIS (1 << 16)
#define PLLP_OUT4_RSTN_EN (0 << 16)
#define PLLP_OUT4_CLKEN (1 << 17)
#define PLLP_OUT4_OVRRIDE (1 << 18)
enum {
IN_408_OUT_204_DIVISOR = 2,
IN_408_OUT_102_DIVISOR = 6,
IN_408_OUT_48_DIVISOR = 15,
IN_408_OUT_9_6_DIVISOR = 83,
};
/* PLLX_BASE_0 0xe0 */
#define PLLX_BASE_PLLX_ENABLE (1 << 30)
@ -453,56 +430,39 @@ enum {
#define SCLK_COP_IRQ_MASK (1 << 25)
#define SCLK_CPU_IRQ_MASK (1 << 24)
#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12
#define SCLK_SWAKEUP_FIQ_SOURCE_MASK \
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8
#define SCLK_SWAKEUP_IRQ_SOURCE_MASK \
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4
#define SCLK_SWAKEUP_RUN_SOURCE_MASK \
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0
#define SCLK_SWAKEUP_IDLE_SOURCE_MASK \
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
#define SCLK_FIQ_SHIFT 12
#define SCLK_FIQ_MASK (7 << SCLK_FIQ_SHIFT)
#define SCLK_IRQ_SHIFT 8
#define SCLK_IRQ_MASK (7 << SCLK_FIQ_SHIFT)
#define SCLK_RUN_SHIFT 4
#define SCLK_RUN_MASK (7 << SCLK_FIQ_SHIFT)
#define SCLK_IDLE_SHIFT 0
#define SCLK_IDLE_MASK (7 << SCLK_FIQ_SHIFT)
enum {
SCLK_SOURCE_CLKM,
SCLK_SOURCE_PLLC_OUT1,
SCLK_SOURCE_PLLP_OUT4,
SCLK_SOURCE_PLLP_OUT3,
SCLK_SOURCE_PLLP_OUT2,
SCLK_SOURCE_CLKD,
SCLK_SOURCE_PLLC_OUT0,
SCLK_SOURCE_CLKS,
SCLK_SOURCE_PLLM_OUT1,
};
#define SCLK_SWAKE_FIQ_SRC_CLKM (0 << 12)
#define SCLK_SWAKE_IRQ_SRC_CLKM (0 << 8)
#define SCLK_SWAKE_RUN_SRC_CLKM (0 << 4)
#define SCLK_SWAKE_IDLE_SRC_CLKM (0 << 0)
#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12)
#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8)
#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4)
#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2c */
#define SUPER_SCLK_ENB_SHIFT 31U
#define SUPER_SCLK_ENB_MASK (1U << 31)
#define SUPER_SCLK_DIVIDEND_SHIFT 8
#define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT)
#define SUPER_SCLK_DIVISOR_SHIFT 0
#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT)
#define SCLK_DIV_ENB (1 << 31)
#define SCLK_DIVIDEND_SHIFT 8
#define SCLK_DIVIDEND_MASK (0xff << SCLK_DIVIDEND_SHIFT)
#define SCLK_DIVISOR_SHIFT 0
#define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT)
/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
#define CLK_SYS_RATE_AHB_RATE_SHIFT 4
#define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
#define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
#define CLK_SYS_RATE_APB_RATE_SHIFT 0
#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
#define HCLK_DISABLE (1 << 7)
#define HCLK_DIVISOR_SHIFT 4
#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
#define PCLK_DISABLE (1 << 3)
#define PCLK_DIVISOR_SHIFT 0
#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29)

View File

@ -20,8 +20,8 @@
#include <soc/clock.h>
#include <stdlib.h>
#include "clk_rst.h"
#include "cpug.h"
#include "flow.h"
#include "maincpu.h"
#include "pmc.h"
#include "sysctr.h"
@ -79,7 +79,8 @@ union __attribute__((transparent_union)) pll_fields {
/* This table defines the frequency dividers for every PLL to turn the external
* OSC clock into the frequencies defined by TEGRA_PLL*_KHZ in soc/clock.h.
* All PLLs have three dividers (N, M and P), with the governing formula for
* the output frequency being OUT = (IN / m) * N / (2^P). */
* the output frequency being OUT = (IN / m) * N / (2^P).
* Yes, it really is one equation with three unknowns ... */
struct {
int khz;
struct pllcx_dividers pllx; /* target: 1900 MHz */
@ -87,62 +88,78 @@ struct {
struct pllcx_dividers pllc; /* target: 600 MHz */
struct pllpad_dividers plld; /* target: 925 MHz */
struct pllu_dividers pllu; /* target; 960 MHz */
struct pllcx_dividers plldp; /* target; 270 MHz */
struct pllcx_dividers plld2; /* target; 570 MHz */
} static const osc_table[16] = {
[OSC_FREQ_OSC12]{
.khz = 12000,
.pllx = {.n = 158, .m = 1, .p = 0}, /* 1896 MHz */
.pllp = {.n = 34, .m = 1, .p = 0, .cpcon = 2},
.pllc = {.n = 50, .m = 1, .p = 0},
.plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12},
.plld = {.n = 283, .m = 12, .p = 0, .cpcon = 8}, /* 283 MHz */
.pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3},
.plldp = {.n = 90, .m = 1, .p = 3}, /* 270 MHz */
.plld2 = {.n = 95, .m = 1, .p = 1}, /* 570 MHz */
},
[OSC_FREQ_OSC13]{
.khz = 13000,
.pllx = {.n = 146, .m = 1, .p = 0}, /* 1898 MHz */
.pllp = {.n = 408, .m = 13, .p = 0, .cpcon = 8},
.pllc = {.n = 231, .m = 5, .p = 0}, /* 600.6 MHz */
.plld = {.n = 925, .m = 13, .p = 0, .cpcon = 12},
.plld = {.n = 283, .m = 13, .p = 0, .cpcon = 8}, /* 283 MHz*/
.pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12},
.plldp = {.n = 83, .m = 1, .p = 3}, /* 269.75 MHz */
.plld2 = {.n = 88, .m = 1, .p = 1}, /* 572 MHz */
},
[OSC_FREQ_OSC16P8]{
.khz = 16800,
.pllx = {.n = 113, .m = 1, .p = 0}, /* 1898.4 MHz */
.pllp = {.n = 170, .m = 7, .p = 0, .cpcon = 4},
.pllc = {.n = 250, .m = 7, .p = 0},
.plld = {.n = 936, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
.plld = {.n = 286, .m = 17, .p = 0, .cpcon = 8}, /* 282.6 MHz*/
.pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 8},
.plldp = {.n = 64, .m = 1, .p = 3}, /* 268.8 MHz */
.plld2 = {.n = 68, .m = 1, .p = 1}, /* 571.2 MHz */
},
[OSC_FREQ_OSC19P2]{
.khz = 19200,
.pllx = {.n = 98, .m = 1, .p = 0}, /* 1881.6 MHz */
.pllp = {.n = 85, .m = 4, .p = 0, .cpcon = 3},
.pllc = {.n = 125, .m = 4, .p = 0},
.plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
.plld = {.n = 251, .m = 17, .p = 0, .cpcon = 8}, /* 283.5 MHz */
.pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2},
.plldp = {.n = 56, .m = 1, .p = 3}, /* 270.75 MHz */
.plld2 = {.n = 59, .m = 1, .p = 1}, /* 570 MHz */
},
[OSC_FREQ_OSC26]{
.khz = 26000,
.pllx = {.n = 73, .m = 1, .p = 0}, /* 1898 MHz */
.pllp = {.n = 204, .m = 13, .p = 0, .cpcon = 5},
.pllc = {.n = 23, .m = 1, .p = 0}, /* 598 MHz */
.plld = {.n = 925, .m = 26, .p = 0, .cpcon = 12},
.plld = {.n = 283, .m = 26, .p = 0, .cpcon = 8}, /* 283 MHz */
.pllu = {.n = 480, .m = 13, .p = 0, .cpcon = 8},
.plldp = {.n = 83, .m = 2, .p = 3}, /* 266.50 MHz */
.plld2 = {.n = 88, .m = 2, .p = 1}, /* 570 MHz */
},
[OSC_FREQ_OSC38P4]{
.khz = 38400,
.pllx = {.n = 98, .m = 1, .p = 0}, /* 1881.6 MHz */
.pllp = {.n = 85, .m = 4, .p = 0, .cpcon = 3},
.pllc = {.n = 125, .m = 4, .p = 0},
.plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
.plld = {.n = 125, .m = 17, .p = 0, .cpcon = 8}, /* 282.4 MHz */
.pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2},
.plldp = {.n = 56, .m = 2, .p = 3}, /* 268 MHz */
.plld2 = {.n = 59, .m = 2, .p = 1}, /* 566 MHz */
},
[OSC_FREQ_OSC48]{
.khz = 48000,
.pllx = {.n = 158, .m = 1, .p = 0}, /* 1896 MHz */
.pllp = {.n = 24, .m = 1, .p = 0, .cpcon = 2},
.pllc = {.n = 50, .m = 1, .p = 0},
.plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12},
.plld = {.n = 71, .m = 12, .p = 0, .cpcon = 8}, /* 284 MHz */
.pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3},
.plldp = {.n = 90, .m = 4, .p = 3}, /* 264 MHz */
.plld2 = {.n = 95, .m = 4, .p = 1}, /* 570 MHz */
},
};
@ -174,19 +191,23 @@ void clock_init_arm_generic_timer(void)
write32(cntcr, &sysctr->cntcr);
}
static void adjust_pllp_out_freqs(void)
{
u32 reg;
/* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
reg = readl(&clk_rst->pllp_outa); // OUTA contains OUT2 / OUT1
reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
writel(reg, &clk_rst->pllp_outa);
#define SOR0_CLK_SEL0 (1 << 14)
#define SOR0_CLK_SEL1 (1 << 15)
reg = readl(&clk_rst->pllp_outb); // OUTB, contains OUT4 / OUT3
reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
writel(reg, &clk_rst->pllp_outb);
void sor_clock_stop(void)
{
/* The Serial Output Resource clock has to be off
* before we start the plldp. Learned the hard way.
* FIXME: this has to be cleaned up a bit more.
* Waiting on some new info from Nvidia.
*/
clrbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1);
}
void sor_clock_start(void)
{
/* uses PLLP, has a non-standard bit layout. */
setbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0);
}
static void init_pll(u32 *base, u32 *misc, const union pll_fields pll)
@ -197,7 +218,6 @@ static void init_pll(u32 *base, u32 *misc, const union pll_fields pll)
/* Write dividers but BYPASS the PLL while we're messing with it. */
writel(dividers | PLL_BASE_BYPASS, base);
/* Set CPCON field (defaults to 0 if it doesn't exist for this PLL) */
writel(pll.div.cpcon << PLL_MISC_CPCON_SHIFT, misc);
@ -237,6 +257,41 @@ static void init_utmip_pll(void)
setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
}
/* Graphics just has to be different. There's a few more bits we
* need to set in here, but it makes sense just to restrict all the
* special bits to this one function.
*/
static void graphics_pll(void)
{
int osc = clock_get_osc_bits();
u32 *cfg = &clk_rst->plldp_ss_cfg;
/* the vendor code sets the dither bit (28)
* an undocumented bit (24)
* and clamp while we mess with it (22)
* Dither is pretty important to display port
* so we really do need to handle these bits.
* I'm not willing to not clamp it, even if
* it might "mostly work" with it not set,
* I don't want to find out in a few months
* that it is needed.
*/
u32 scfg = (1<<28) | (1<<24) | (1<<22);
writel(scfg, cfg);
init_pll(&clk_rst->plldp_base, &clk_rst->plldp_misc, osc_table[osc].plldp);
/* leave dither and undoc bits set, release clamp */
scfg = (1<<28) | (1<<24);
writel(scfg, cfg);
/* set lock bit */
setbits_le32(&clk_rst->plldp_misc, PLLDPD2_MISC_LOCK_ENABLE);
/* init clock source for disp1 */
/* init plld (the actual output is plld_out0 that is 1/2 of plld. */
init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, osc_table[osc].plld);
setbits_le32(&clk_rst->plld_misc, PLLUD_MISC_LOCK_ENABLE);
setbits_le32(&clk_rst->plld_misc, PLLD_MISC_CLK_ENABLE);
udelay(10); /* wait for plld ready */
}
/* Initialize the UART and put it on CLK_M so we can use it during clock_init().
* Will later move it to PLLP in clock_config(). The divisor must be very small
* to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1
@ -252,13 +307,36 @@ void clock_early_uart(void)
clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA);
}
/* Enable output clock (CLK1~3) for external peripherals. */
void clock_external_output(int clk_id)
{
switch (clk_id) {
case 1:
setbits_le32(&pmc->clk_out_cntrl, 1 << 2);
break;
case 2:
setbits_le32(&pmc->clk_out_cntrl, 1 << 10);
break;
case 3:
setbits_le32(&pmc->clk_out_cntrl, 1 << 18);
break;
default:
printk(BIOS_CRIT, "ERROR: Unknown output clock id %d\n",
clk_id);
break;
}
}
void clock_cpu0_config_and_reset(void *entry)
{
void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100;
write32(CONFIG_STACK_TOP, &cpug_stack_pointer);
write32((uintptr_t)entry, &cpug_entry_point);
write32((uintptr_t)&cpug_setup, evp_cpu_reset);
write32(CONFIG_STACK_TOP, &maincpu_stack_pointer);
write32((uintptr_t)entry, &maincpu_entry_point);
write32((uintptr_t)&maincpu_setup, evp_cpu_reset);
/* Set active CPU cluster to G */
clrbits_le32(&flow->cluster_control, 1);
// Set up cclk_brst and divider.
write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) |
@ -296,75 +374,82 @@ void clock_cpu0_config_and_reset(void *entry)
&clk_rst->rst_cpug_cmplx_clr);
}
/**
* The T124 requires some special clock initialization, including setting up
* the DVC I2C, turning on MSELECT and selecting the G CPU cluster
*/
void clock_halt_avp(void)
{
for (;;) {
write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ |
FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
&flow->halt_cop_events);
}
}
void clock_init(void)
{
u32 val;
u32 osc = clock_get_osc_bits();
/*
* On poweron, AVP clock source (also called system clock) is set to
* PLLP_out0 with frequency set at 1MHz. Before initializing PLLP, we
* need to move the system clock's source to CLK_M temporarily. And
* then switch it to PLLP_out4 (204MHz) at a later time.
*/
val = (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
(SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
(SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
(SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
writel(val, &clk_rst->sclk_brst_pol);
udelay(2);
/* Set active CPU cluster to G */
clrbits_le32(&flow->cluster_control, 1);
/* Change the oscillator drive strength */
val = readl(&clk_rst->osc_ctrl);
val &= ~OSC_XOFS_MASK;
val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
writel(val, &clk_rst->osc_ctrl);
/* Ambiguous quote from u-boot. TODO: what's this mean?
* "should update same value in PMC_OSC_EDPD_OVER XOFS
field for warmboot "*/
val = readl(&pmc->osc_edpd_over);
val &= ~PMC_OSC_EDPD_OVER_XOFS_MASK;
val |= (OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
writel(val, &pmc->osc_edpd_over);
/* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */
val = readl(&clk_rst->pllx_misc3);
val &= ~PLLX_IDDQ_MASK;
writel(val, &clk_rst->pllx_misc3);
udelay(2);
/* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */
writel(0x2b << 17 | 0xb << 9, &clk_rst->pllc_misc2);
adjust_pllp_out_freqs();
/* Max out the AVP clock before everything else (need PLLC for that). */
init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, osc_table[osc].pllc);
/* Be more careful with processor clock, wait for the lock. (~10us) */
setbits_le32(&clk_rst->pllc_misc, PLLC_MISC_LOCK_ENABLE);
while (!(read32(&clk_rst->pllc_base) & PLL_BASE_LOCK)) /* wait */;
/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
* features section in the TRM). */
write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT,
&clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */
write32(0 << SCLK_DIVIDEND_SHIFT |
(CEIL_DIV(TEGRA_PLLC_KHZ, 300000) - 1) << SCLK_DIVISOR_SHIFT
| SCLK_DIV_ENB, &clk_rst->super_sclk_div);
write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT |
SCLK_SOURCE_PLLC_OUT0 << SCLK_RUN_SHIFT,
&clk_rst->sclk_brst_pol); /* sclk = 300 MHz */
/* Change the oscillator drive strength (from U-Boot -- why?) */
clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK,
OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
/*
* Ambiguous quote from u-boot. TODO: what's this mean?
* "should update same value in PMC_OSC_EDPD_OVER XOFS
* field for warmboot "
*/
clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK,
OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
/* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */
clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK);
/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT |
(CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
&clk_rst->pllp_outa);
write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT |
(CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
&clk_rst->pllp_outb);
init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, osc_table[osc].pllx);
init_pll(&clk_rst->pllp_base, &clk_rst->pllp_misc, osc_table[osc].pllp);
init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, osc_table[osc].pllc);
init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, osc_table[osc].plld);
init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, osc_table[osc].pllu);
init_utmip_pll();
val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
writel(val, &clk_rst->clk_sys_rate);
graphics_pll();
}
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w)
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
{
if (l) writel(l, &clk_rst->clk_enb_l_set);
if (h) writel(h, &clk_rst->clk_enb_h_set);
if (u) writel(u, &clk_rst->clk_enb_u_set);
if (v) writel(v, &clk_rst->clk_enb_v_set);
if (w) writel(w, &clk_rst->clk_enb_w_set);
if (x) writel(x, &clk_rst->clk_enb_x_set);
/* Give clocks time to stabilize. */
udelay(IO_STABILIZATION_DELAY);
@ -374,4 +459,5 @@ void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w)
if (u) writel(u, &clk_rst->rst_dev_u_clr);
if (v) writel(v, &clk_rst->rst_dev_v_clr);
if (w) writel(w, &clk_rst->rst_dev_w_clr);
if (x) writel(x, &clk_rst->rst_dev_x_clr);
}

View File

@ -87,7 +87,7 @@ static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
};
static int update_display_mode(struct dc_disp_reg *disp,
struct soc_nvidia_tegra124_config *config)
struct soc_nvidia_tegra124_config *config)
{
u32 val;
u32 rate;
@ -315,7 +315,7 @@ void display_startup(device_t dev)
{ u16 *cp = (void *)(framebuffer_base_mb*MiB);
for(i = 0; i < 1048576*8; i++)
if (i %(2560/2) < 1280/2)
if (i % (1376 / 2) < 688 / 2)
cp[i] = 0x222;
else
cp[i] = 0x888;
@ -324,9 +324,9 @@ void display_startup(device_t dev)
/* tell depthcharge ...
*/
struct edid edid;
edid.x_resolution = 2560;
edid.y_resolution = 1700;
edid.bytes_per_line = 2560 * 2;
edid.x_resolution = 1376;
edid.y_resolution = 768;
edid.bytes_per_line = 1376 * 2;
edid.framebuffer_bits_per_pixel = 16;
set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB));

View File

@ -37,9 +37,7 @@
#include "chip.h"
#include "sor.h"
#include <soc/display.h>
#include <soc/ardisplay.h>
#include <soc/arsor.h>
#include <soc/ardpaux.h>
//#include <soc/nvidia/tegra/displayport.h>
extern int dump;
unsigned long READL(void *p);
@ -50,29 +48,7 @@ int dpaux_read(u32 addr, u32 size, u8 * data);
void init_dca_regs(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE;
// u32 val;
printk(BIOS_SPEW, "JZ: %s: entry\n", __func__);
#define SWR_DISP1_RST (1 << 27)
#define SWR_HOST1X_RST (1 << 28)
#define CLK_ENB_DISP1 SWR_DISP1_RST
#define CLK_ENB_HOST1X SWR_HOST1X_RST
// REG(CLK_RST_CONTROLLER_RST_DEVICES_L_0, SWR_DISP1_RST, 1);
// REG(CLK_RST_CONTROLLER_RST_DEVICES_L_0, SWR_DISP1_RST, 0);
// REG(CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0, CLK_ENB_DISP1, 1);
/* enable disp1 */
setbits_le32(&clkrst->rst_dev_l, SWR_DISP1_RST); // Set Reset
clrbits_le32(&clkrst->rst_dev_l, SWR_DISP1_RST); // Clear Reset
setbits_le32(&clkrst->clk_out_enb_l, CLK_ENB_DISP1); // Set Enable
WRITEL(0x00000000, (void *)(0x60006000 + 0x138)); // CLK_SOURCE_DISP1 = PLLP
// WRITEL(0x40000000, (void *)(0x60006000 + 0x138)); // CLK_SOURCE_DISP1 = PLLD
/* enable host1x */
clrbits_le32(&clkrst->rst_dev_l, SWR_HOST1X_RST); // Clear Reset
setbits_le32(&clkrst->clk_out_enb_l, CLK_ENB_HOST1X); // Set Enable
WRITEL(0x80000000, (void *)(0x60006000 + 0x180)); // CLK_SOURCE_HOST1X = PLLP
// WRITEL(0x40000000, (0x60006000 + 0x180)); // CLK_SOURCE_HOST1X = PLLC
printk(BIOS_SPEW, "%s: entry\n", __func__);
#if 1
#define DCA_WRITE(reg, val) \
@ -98,291 +74,46 @@ void init_dca_regs(void)
}
#endif
DCA_WRITE(DC_DISP_DISP_CLOCK_CONTROL_0, 0x00000006); //0x542410b8
DCA_WRITE(DC_CMD_INT_STATUS_0, 0xffffffff); //0x542400dc
DCA_WRITE(DC_CMD_INT_MASK_0, 0x00000000); //0x542400e0
DCA_WRITE(DC_CMD_INT_ENABLE_0, 0x00800701); //0x542400e4
DCA_WRITE(DC_CMD_INT_POLARITY_0, 0x00c00706); //0x542400ec
DCA_WRITE(DC_DISP_DISP_SIGNAL_OPTIONS0_0, 0x00000000); //0x54241000
DCA_WRITE(DC_DISP_DISP_SIGNAL_OPTIONS1_0, 0x00000000); //0x54241004
DCA_WRITE(DC_DISP_DISP_WIN_OPTIONS_0, 0x00000000); //0x54241008
DCA_WRITE(DC_DISP_MEM_HIGH_PRIORITY_0, 0x00000000); //0x5424100c
DCA_WRITE(DC_DISP_MEM_HIGH_PRIORITY_TIMER_0, 0x00000000); //0x54241010
DCA_WRITE(DC_DISP_DISP_TIMING_OPTIONS_0, 0x00000000); //0x54241014
DCA_WRITE(DC_DISP_REF_TO_SYNC_0, 0x00000000); //0x54241018
DCA_WRITE(DC_DISP_SYNC_WIDTH_0, 0x00000000); //0x5424101c
DCA_WRITE(DC_DISP_BACK_PORCH_0, 0x00000000); //0x54241020
DCA_WRITE(DC_DISP_DISP_ACTIVE_0, 0x00030003); //0x54241024
DCA_WRITE(DC_DISP_FRONT_PORCH_0, 0x00000000); //0x54241028
DCA_WRITE(DC_DISP_H_PULSE0_CONTROL_0, 0x00000000); //0x5424102c
DCA_WRITE(DC_DISP_H_PULSE0_POSITION_A_0, 0x00000000); //0x54241030
DCA_WRITE(DC_DISP_H_PULSE0_POSITION_B_0, 0x00000000); //0x54241034
DCA_WRITE(DC_DISP_H_PULSE0_POSITION_C_0, 0x00000000); //0x54241038
DCA_WRITE(DC_DISP_H_PULSE0_POSITION_D_0, 0x00000000); //0x5424103c
DCA_WRITE(DC_DISP_H_PULSE1_CONTROL_0, 0x00000000); //0x54241040
DCA_WRITE(DC_DISP_H_PULSE1_POSITION_A_0, 0x00000000); //0x54241044
DCA_WRITE(DC_DISP_H_PULSE1_POSITION_B_0, 0x00000000); //0x54241048
DCA_WRITE(DC_DISP_H_PULSE1_POSITION_C_0, 0x00000000); //0x5424104c
DCA_WRITE(DC_DISP_H_PULSE1_POSITION_D_0, 0x00000000); //0x54241050
DCA_WRITE(DC_DISP_H_PULSE2_CONTROL_0, 0x00000000); //0x54241054
DCA_WRITE(DC_DISP_H_PULSE2_POSITION_A_0, 0x00000000); //0x54241058
DCA_WRITE(DC_DISP_H_PULSE2_POSITION_B_0, 0x00000000); //0x5424105c
DCA_WRITE(DC_DISP_H_PULSE2_POSITION_C_0, 0x00000000); //0x54241060
DCA_WRITE(DC_DISP_H_PULSE2_POSITION_D_0, 0x00000000); //0x54241064
DCA_WRITE(DC_DISP_V_PULSE0_CONTROL_0, 0x00000000); //0x54241068
DCA_WRITE(DC_DISP_V_PULSE0_POSITION_A_0, 0x00000000); //0x5424106c
DCA_WRITE(DC_DISP_V_PULSE0_POSITION_B_0, 0x00000000); //0x54241070
DCA_WRITE(DC_DISP_V_PULSE0_POSITION_C_0, 0x00000000); //0x54241074
DCA_WRITE(DC_DISP_V_PULSE1_CONTROL_0, 0x00000000); //0x54241078
DCA_WRITE(DC_DISP_V_PULSE1_POSITION_A_0, 0x00000000); //0x5424107c
DCA_WRITE(DC_DISP_V_PULSE1_POSITION_B_0, 0x00000000); //0x54241080
DCA_WRITE(DC_DISP_V_PULSE1_POSITION_C_0, 0x00000000); //0x54241084
DCA_WRITE(DC_DISP_V_PULSE2_CONTROL_0, 0x00000000); //0x54241088
DCA_WRITE(DC_DISP_V_PULSE2_POSITION_A_0, 0x00000000); //0x5424108c
DCA_WRITE(DC_DISP_V_PULSE3_CONTROL_0, 0x00000000); //0x54241090
DCA_WRITE(DC_DISP_V_PULSE3_POSITION_A_0, 0x00000000); //0x54241094
DCA_WRITE(DC_DISP_M0_CONTROL_0, 0x00000000); //0x54241098
DCA_WRITE(DC_DISP_M1_CONTROL_0, 0x00000000); //0x5424109c
DCA_WRITE(DC_DISP_DI_CONTROL_0, 0x00000000); //0x542410a0
DCA_WRITE(DC_DISP_PP_CONTROL_0, 0x00000000); //0x542410a4
DCA_WRITE(DC_DISP_PP_SELECT_A_0, 0x00000000); //0x542410a8
DCA_WRITE(DC_DISP_PP_SELECT_B_0, 0x00000000); //0x542410ac
DCA_WRITE(DC_DISP_PP_SELECT_C_0, 0x00000000); //0x542410b0
DCA_WRITE(DC_DISP_PP_SELECT_D_0, 0x00000000); //0x542410b4
DCA_WRITE(DC_DISP_DISP_INTERFACE_CONTROL_0, 0x00000000); //0x542410bc
DCA_WRITE(DC_DISP_DISP_COLOR_CONTROL_0, 0x00000000); //0x542410c0
DCA_WRITE(DC_DISP_SHIFT_CLOCK_OPTIONS_0, 0x00000000); //0x542410c4
DCA_WRITE(DC_DISP_DATA_ENABLE_OPTIONS_0, 0x00000000); //0x542410c8
DCA_WRITE(DC_DISP_SERIAL_INTERFACE_OPTIONS_0, 0x00000000); //0x542410cc
DCA_WRITE(DC_DISP_LCD_SPI_OPTIONS_0, 0x00000000); //0x542410d0
DCA_WRITE(DC_DISP_COLOR_KEY0_LOWER_0, 0x00000000); //0x542410d8
DCA_WRITE(DC_DISP_COLOR_KEY0_UPPER_0, 0x00000000); //0x542410dc
DCA_WRITE(DC_DISP_COLOR_KEY1_LOWER_0, 0x00000000); //0x542410e0
DCA_WRITE(DC_DISP_COLOR_KEY1_UPPER_0, 0x00000000); //0x542410e4
DCA_WRITE(DC_DISP_CURSOR_FOREGROUND_0, 0x00000000); //0x542410f0
DCA_WRITE(DC_DISP_CURSOR_BACKGROUND_0, 0x00000000); //0x542410f4
DCA_WRITE(DC_DISP_CURSOR_START_ADDR_0, 0x00200000); //0x542410f8
DCA_WRITE(DC_DISP_CURSOR_START_ADDR_NS_0, 0x00000000); //0x542410fc
DCA_WRITE(DC_DISP_CURSOR_POSITION_0, 0x00000000); //0x54241100
DCA_WRITE(DC_DISP_CURSOR_POSITION_NS_0, 0x00000000); //0x54241104
DCA_WRITE(DC_DISP_INIT_SEQ_CONTROL_0, 0x00000000); //0x54241108
DCA_WRITE(DC_DISP_SPI_INIT_SEQ_DATA_A_0, 0x00000000); //0x5424110c
DCA_WRITE(DC_DISP_SPI_INIT_SEQ_DATA_B_0, 0x00000000); //0x54241110
DCA_WRITE(DC_DISP_SPI_INIT_SEQ_DATA_C_0, 0x00000000); //0x54241114
DCA_WRITE(DC_DISP_SPI_INIT_SEQ_DATA_D_0, 0x00000000); //0x54241118
DCA_WRITE(DC_DISP_DC_MCCIF_FIFOCTRL_0, 0x00000000); //0x54241200
DCA_WRITE(DC_DISP_MCCIF_DISPLAY0A_HYST_0, 0xcf401f1f); //0x54241204
DCA_WRITE(DC_DISP_MCCIF_DISPLAY0B_HYST_0, 0xcf401f1f); //0x54241208
DCA_WRITE(DC_DISP_MCCIF_DISPLAY0C_HYST_0, 0xcf401f1f); //0x5424120c
DCA_WRITE(DC_DISP_DISP_MISC_CONTROL_0, 0x00000002); //0x54241304
DCA_WRITE(DC_DISP_SD_CONTROL_0, 0x00004000); //0x54241308
DCA_WRITE(DC_DISP_SD_CSC_COEFF_0, 0x00000000); //0x5424130c
DCA_WRITE (DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x000000F0);
DCA_WRITE (DC_WIN_A_WIN_OPTIONS_0, 0x00000000);
DCA_WRITE (DC_WIN_A_BYTE_SWAP_0, 0x00000000);
DCA_WRITE (DC_WIN_A_BUFFER_CONTROL_0, 0x00000000);
DCA_WRITE (DC_WIN_A_COLOR_DEPTH_0, 0x0000000C);
DCA_WRITE(DC_DISP_SD_LUT_0, 0x00000000); //0x54241310
#define DC_DISP_SD_LUT_1_0 0x4c5
#define DC_DISP_SD_LUT_2_0 0x4c6
#define DC_DISP_SD_LUT_3_0 0x4c7
#define DC_DISP_SD_LUT_4_0 0x4c8
#define DC_DISP_SD_LUT_5_0 0x4c9
#define DC_DISP_SD_LUT_6_0 0x4ca
#define DC_DISP_SD_LUT_7_0 0x4cb
#define DC_DISP_SD_LUT_8_0 0x4cc
DCA_WRITE(DC_DISP_SD_LUT_1_0, 0x00000000); //0x54241314
DCA_WRITE(DC_DISP_SD_LUT_2_0, 0x00000000); //0x54241318
DCA_WRITE(DC_DISP_SD_LUT_3_0, 0x00000000); //0x5424131c
DCA_WRITE(DC_DISP_SD_LUT_4_0, 0x00000000); //0x54241320
DCA_WRITE(DC_DISP_SD_LUT_5_0, 0x00000000); //0x54241324
DCA_WRITE(DC_DISP_SD_LUT_6_0, 0x00000000); //0x54241328
DCA_WRITE(DC_DISP_SD_LUT_7_0, 0x00000000); //0x5424132c
DCA_WRITE(DC_DISP_SD_LUT_8_0, 0x00000000); //0x54241330
DCA_WRITE(DC_DISP_SD_FLICKER_CONTROL_0, 0x00000000); //0x54241334
DCA_WRITE(DC_DISP_SD_PIXEL_COUNT_0, 0x00000000); //0x54241338
DCA_WRITE (DC_WIN_A_POSITION_0, 0x00000000);
DCA_WRITE (DC_WIN_A_SIZE_0, 0x00000000);
DCA_WRITE (DC_WIN_A_PRESCALED_SIZE_0, 0x00000000);
DCA_WRITE (DC_WIN_A_H_INITIAL_DDA_0, 0x00000000);
DCA_WRITE (DC_WIN_A_V_INITIAL_DDA_0, 0x00000000);
DCA_WRITE (DC_WIN_A_DDA_INCREMENT_0, 0x00000000);
DCA_WRITE (DC_WIN_A_LINE_STRIDE_0, 0x00000000);
DCA_WRITE (DC_WIN_A_DV_CONTROL_0, 0x00000000);
DCA_WRITE(DC_DISP_SD_HISTOGRAM_0, 0x00000000); //0x5424133c
#define DC_DISP_SD_HISTOGRAM_1_0 0x4d0
#define DC_DISP_SD_HISTOGRAM_2_0 0x4d1
#define DC_DISP_SD_HISTOGRAM_3_0 0x4d2
#define DC_DISP_SD_HISTOGRAM_4_0 0x4d3
#define DC_DISP_SD_HISTOGRAM_5_0 0x4d4
#define DC_DISP_SD_HISTOGRAM_6_0 0x4d5
#define DC_DISP_SD_HISTOGRAM_7_0 0x4d6
DCA_WRITE(DC_DISP_SD_HISTOGRAM_1_0, 0x00000000); //0x54241340
DCA_WRITE(DC_DISP_SD_HISTOGRAM_2_0, 0x00000000); //0x54241344
DCA_WRITE(DC_DISP_SD_HISTOGRAM_3_0, 0x00000000); //0x54241348
DCA_WRITE(DC_DISP_SD_HISTOGRAM_4_0, 0x00000000); //0x5424134c
DCA_WRITE(DC_DISP_SD_HISTOGRAM_5_0, 0x00000000); //0x54241350
DCA_WRITE(DC_DISP_SD_HISTOGRAM_6_0, 0x00000000); //0x54241354
DCA_WRITE(DC_DISP_SD_HISTOGRAM_7_0, 0x00000000); //0x54241358
DCA_WRITE(DC_DISP_SD_BL_PARAMETERS_0, 0x00000400); //0x5424135c
DCA_WRITE(DC_DISP_SD_BL_TF_0, 0x00000000); //0x54241360
#define DC_DISP_SD_BL_TF_1_0 0x4d9
#define DC_DISP_SD_BL_TF_2_0 0x4da
#define DC_DISP_SD_BL_TF_3_0 0x4db
DCA_WRITE(DC_DISP_SD_BL_TF_1_0, 0x00000000); //0x54241364
DCA_WRITE(DC_DISP_SD_BL_TF_2_0, 0x00000000); //0x54241368
DCA_WRITE(DC_DISP_SD_BL_TF_3_0, 0x00000000); //0x5424136c
DCA_WRITE(DC_DISP_SD_BL_CONTROL_0, 0x00000000); //0x54241370
DCA_WRITE(DC_DISP_SD_HW_K_VALUES_0, 0x00000000); //0x54241374
DCA_WRITE(DC_DISP_SD_MAN_K_VALUES_0, 0x00000000); //0x54241378
DCA_WRITE(DC_DISP_SD_K_LIMIT_0, 0x00000000); //0x5424137c
DCA_WRITE(DC_DISP_SD_WINDOW_POSITION_0, 0x00000000); //0x54241380
DCA_WRITE(DC_DISP_SD_WINDOW_SIZE_0, 0x00000000); //0x54241384
DCA_WRITE(DC_DISP_SD_SOFT_CLIPPING_0, 0x02000080); //0x54241388
DCA_WRITE(DC_DISP_SD_SMOOTH_K_0, 0x00000000); //0x5424138c
DCA_WRITE(DC_DISP_BLEND_BACKGROUND_COLOR_0, 0x00000000); //0x54241390
DCA_WRITE(DC_DISP_INTERLACE_CONTROL_0, 0x00000000); //0x54241394
DCA_WRITE(DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0, 0x00000000); //0x54241398
DCA_WRITE(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0, 0x00000000); //0x5424139c
DCA_WRITE(DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0, 0x00000000); //0x542413a0
DCA_WRITE(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0, 0x00000000); //0x542413a4
DCA_WRITE(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0, 0x00000000); //0x542413a8
DCA_WRITE(DC_DISP_CURSOR_UNDERFLOW_CTRL_0, 0x00000000); //0x542413ac
DCA_WRITE(DC_DISP_CURSOR_START_ADDR_HI_0, 0x00000000); //0x542413b0
DCA_WRITE(DC_DISP_CURSOR_START_ADDR_HI_NS_0, 0x00000000); //0x542413b4
DCA_WRITE(DC_DISP_CURSOR_INTERLACE_CONTROL_0, 0x00000000); //0x542413b8
DCA_WRITE(DC_DISP_CSC2_CONTROL_0, 0x00000000); //0x542413bc
DCA_WRITE(DC_DISP_BLEND_CURSOR_CONTROL_0, 0x00000000); //0x542413c4
DCA_WRITE(DC_DISP_DVFS_CURSOR_CONTROL_0, 0x00000003); //0x542413c8
DCA_WRITE(DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0, 0x00000000); //0x542413cc
DCA_WRITE(DC_DISP_CURSOR_SPOOLUP_CONTROL_0, 0x00000001); //0x542413d0
DCA_WRITE(DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0, 0x00000000); //0x542413d4
DCA_WRITE(DC_DISP_DISPLAY_DBG_TIMING_0, 0x00000000); //0x542413d8
DCA_WRITE(DC_DISP_DISPLAY_SPARE0_0, 0x00000000); //0x542413dc
DCA_WRITE(DC_DISP_DISPLAY_SPARE1_0, 0x00000000); //0x542413e0
DCA_WRITE (DC_WIN_A_BLEND_LAYER_CONTROL_0, 0x01000000);
DCA_WRITE (DC_WIN_A_BLEND_MATCH_SELECT_0, 0x00000000);
DCA_WRITE (DC_WIN_A_BLEND_NOMATCH_SELECT_0, 0x00000000);
DCA_WRITE (DC_WIN_A_BLEND_ALPHA_1BIT_0, 0x00000000);
#define wr32(reg, val) \
WRITEL(val, (void *)reg)
DCA_WRITE (DC_WINBUF_A_START_ADDR_HI_0, 0x00000000);
DCA_WRITE (DC_WINBUF_A_ADDR_H_OFFSET_0, 0x00000000);
DCA_WRITE (DC_WINBUF_A_ADDR_V_OFFSET_0, 0x00000000);
DCA_WRITE (DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x00000000);
wr32((TEGRA_ARM_DISPLAYA + 0x0200), 0x00000000);
wr32((TEGRA_ARM_DISPLAYA + 0x0400), 0x00000000);
DCA_WRITE (DC_COM_CRC_CONTROL_0, 0x00000000);
DCA_WRITE (DC_COM_CRC_CHECKSUM_0, 0x00000000);
DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE0_0, 0x00000000);
DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE1_0, 0x00000000);
DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE2_0, 0x00510104);
DCA_WRITE (DC_COM_PIN_OUTPUT_ENABLE3_0, 0x00000555);
DCA_WRITE(DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x000000F0);
DCA_WRITE(DC_WIN_A_WIN_OPTIONS_0, 0x00000000);
DCA_WRITE(DC_WIN_A_BYTE_SWAP_0, 0x00000000);
DCA_WRITE(DC_WIN_A_BUFFER_CONTROL_0, 0x00000000);
DCA_WRITE(DC_WIN_A_COLOR_DEPTH_0, 0x0000000C);
DCA_WRITE(DC_WIN_A_POSITION_0, 0x00000000);
DCA_WRITE(DC_WIN_A_SIZE_0, 0x00000000);
DCA_WRITE(DC_WIN_A_PRESCALED_SIZE_0, 0x00000000);
DCA_WRITE(DC_WIN_A_H_INITIAL_DDA_0, 0x00000000);
DCA_WRITE(DC_WIN_A_V_INITIAL_DDA_0, 0x00000000);
DCA_WRITE(DC_WIN_A_DDA_INCREMENT_0, 0x00000000);
DCA_WRITE(DC_WIN_A_LINE_STRIDE_0, 0x00000000);
DCA_WRITE(DC_WIN_A_DV_CONTROL_0, 0x00000000);
DCA_WRITE(DC_WIN_A_BLEND_LAYER_CONTROL_0, 0x01000000);
DCA_WRITE(DC_WIN_A_BLEND_MATCH_SELECT_0, 0x00000000);
DCA_WRITE(DC_WIN_A_BLEND_NOMATCH_SELECT_0, 0x00000000);
DCA_WRITE(DC_WIN_A_BLEND_ALPHA_1BIT_0, 0x00000000);
DCA_WRITE(DC_WINC_A_PALETTE_COLOR_EXT_0, 0x00000000);
DCA_WRITE(DC_WINC_A_CSC_YOF_0, 0x00000000);
DCA_WRITE(DC_WINC_A_CSC_KYRGB_0, 0x00000000);
DCA_WRITE(DC_WINC_A_CSC_KUR_0, 0x00000000);
DCA_WRITE(DC_WINC_A_CSC_KVR_0, 0x00000000);
DCA_WRITE(DC_WINC_A_CSC_KUG_0, 0x00000000);
DCA_WRITE(DC_WINC_A_CSC_KVG_0, 0x00000000);
DCA_WRITE(DC_WINC_A_CSC_KUB_0, 0x00000000);
DCA_WRITE(DC_WINC_A_CSC_KVB_0, 0x00000000);
DCA_WRITE(DC_WINBUF_A_START_ADDR_HI_0, 0x00000000);
DCA_WRITE(DC_WINBUF_A_ADDR_H_OFFSET_0, 0x00000000);
DCA_WRITE(DC_WINBUF_A_ADDR_V_OFFSET_0, 0x00000000);
DCA_WRITE(DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x00000000);
DCA_WRITE(DC_COM_CRC_CONTROL_0, 0x00000000); //0x54240c00
DCA_WRITE(DC_COM_CRC_CHECKSUM_0, 0x00000000); //0x54240c04
DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE0_0, 0x00000000); //0x54240c08
DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE1_0, 0x00000000); //0x54240c0c
DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE2_0, 0x00510104); //0x54240c10
DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE3_0, 0x00000555); //0x54240c14
DCA_WRITE(DC_COM_PIN_OUTPUT_POLARITY0_0, 0x00000000); //0x54240c18
DCA_WRITE(DC_COM_PIN_OUTPUT_POLARITY1_0, 0x00000000); //0x54240c1c
DCA_WRITE(DC_COM_PIN_OUTPUT_POLARITY2_0, 0x00000000); //0x54240c20
DCA_WRITE(DC_COM_PIN_OUTPUT_POLARITY3_0, 0x00000000); //0x54240c24
DCA_WRITE(DC_COM_PIN_OUTPUT_DATA0_0, 0x00000000); //0x54240c28
DCA_WRITE(DC_COM_PIN_OUTPUT_DATA1_0, 0x00000000); //0x54240c2c
DCA_WRITE(DC_COM_PIN_OUTPUT_DATA2_0, 0x00000000); //0x54240c30
DCA_WRITE(DC_COM_PIN_OUTPUT_DATA3_0, 0x00000000); //0x54240c34
DCA_WRITE(DC_COM_PIN_INPUT_DATA0_0, 0x00000000); //0x54240c48
DCA_WRITE(DC_COM_PIN_INPUT_DATA1_0, 0x00000000); //0x54240c4c
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT0_0, 0x00000000); //0x54240c50
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT1_0, 0x00000000); //0x54240c54
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT2_0, 0x00000000); //0x54240c58
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT3_0, 0x00000000); //0x54240c5c
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT4_0, 0x00000000); //0x54240c60
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT5_0, 0x00000000); //0x54240c64
DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT6_0, 0x00000000); //0x54240c68
DCA_WRITE(DC_COM_PIN_MISC_CONTROL_0, 0x00000000); //0x54240c6c
DCA_WRITE(DC_COM_PM0_CONTROL_0, 0x00000000); //0x54240c70
DCA_WRITE(DC_COM_PM0_DUTY_CYCLE_0, 0x00000000); //0x54240c74
DCA_WRITE(DC_COM_PM1_CONTROL_0, 0x00000000); //0x54240c78
DCA_WRITE(DC_COM_PM1_DUTY_CYCLE_0, 0x00000000); //0x54240c7c
DCA_WRITE(DC_COM_SPI_CONTROL_0, 0x00000000); //0x54240c80
DCA_WRITE(DC_COM_SPI_START_BYTE_0, 0x00000000); //0x54240c84
DCA_WRITE(DC_COM_HSPI_WRITE_DATA_AB_0, 0x00000000); //0x54240c88
DCA_WRITE(DC_COM_HSPI_WRITE_DATA_CD_0, 0x00000000); //0x54240c8c
DCA_WRITE(DC_COM_HSPI_CS_DC_0, 0x00000000); //0x54240c90
DCA_WRITE(DC_COM_SCRATCH_REGISTER_A_0, 0x00000000); //0x54240c94
DCA_WRITE(DC_COM_SCRATCH_REGISTER_B_0, 0x00000000); //0x54240c98
DCA_WRITE(DC_COM_CRC_CHECKSUM_LATCHED_0, 0x00000000); //0x54240ca4
DCA_WRITE(DC_COM_CMU_CSC_KRR_0, 0x00000000); //0x54240ca8
DCA_WRITE(DC_COM_CMU_CSC_KGR_0, 0x00000000); //0x54240cac
DCA_WRITE(DC_COM_CMU_CSC_KBR_0, 0x00000000); //0x54240cb0
DCA_WRITE(DC_COM_CMU_CSC_KRG_0, 0x00000000); //0x54240cb4
DCA_WRITE(DC_COM_CMU_CSC_KGG_0, 0x00000000); //0x54240cb8
DCA_WRITE(DC_COM_CMU_CSC_KBG_0, 0x00000000); //0x54240cbc
DCA_WRITE(DC_COM_CMU_CSC_KRB_0, 0x00000000); //0x54240cc0
DCA_WRITE(DC_COM_CMU_CSC_KGB_0, 0x00000000); //0x54240cc4
DCA_WRITE(DC_COM_CMU_CSC_KBB_0, 0x00000000); //0x54240cc8
DCA_WRITE(DC_COM_CMU_LUT_MASK_0, 0x00000000); //0x54240ccc
DCA_WRITE(DC_COM_CMU_LUT1_0, 0x00000000); //0x54240cd8
DCA_WRITE(DC_COM_CMU_LUT2_0, 0x00000000); //0x54240cdc
DCA_WRITE(DC_COM_CMU_LUT1_READ_0, 0x00000000); //0x54240ce0
DCA_WRITE(DC_COM_CMU_LUT2_READ_0, 0x00000000); //0x54240ce4
DCA_WRITE(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240004
DCA_WRITE(DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240008
DCA_WRITE(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240024
DCA_WRITE(DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240028
DCA_WRITE(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240044
DCA_WRITE(DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240048
DCA_WRITE(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240064
DCA_WRITE(DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240068
DCA_WRITE(DC_CMD_CONT_SYNCPT_VSYNC_0, 0x00000000); //0x542400a0
DCA_WRITE(DC_CMD_DISPLAY_COMMAND_OPTION0_0, 0x00000000); //0x542400c4
DCA_WRITE(DC_CMD_DISPLAY_COMMAND_0, 0x00000000); //0x542400c8
DCA_WRITE(DC_CMD_SIGNAL_RAISE_0, 0x00000000); //0x542400cc
DCA_WRITE(DC_CMD_DISPLAY_POWER_CONTROL_0, 0x00000000); //0x542400d8
DCA_WRITE(DC_CMD_SIGNAL_RAISE1_0, 0x00000000); //0x542400f0
DCA_WRITE(DC_CMD_SIGNAL_RAISE2_0, 0x00000000); //0x542400f4
DCA_WRITE(DC_CMD_SIGNAL_RAISE3_0, 0x00000000); //0x542400f8
DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x00000000); //0x54240104
DCA_WRITE(DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x00000000); //0x54240108
DCA_WRITE(DC_CMD_REG_ACT_CONTROL_0, 0x00000000); //0x5424010c
DCA_WRITE(DC_CMD_WIN_T_STATE_CONTROL_0, 0x00000000); //0x54240110
DCA_WRITE(DC_CMD_SECURE_CONTROL_0, 0x00000000); //0x54240114
DCA_WRITE(DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240134
DCA_WRITE(DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240138
printk(BIOS_SPEW, "initial DCA done\n");
}
void init_sor_regs(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE;
printk(BIOS_SPEW, "JZ: %s: entry\n", __func__);
#define SWR_SOR0_RST (1 << 22)
#define CLK_ENB_SOR0 SWR_SOR0_RST
// REG(CLK_RST_CONTROLLER_RST_DEVICES_X_0, SWR_SOR0_RST, 1)
// REG(CLK_RST_CONTROLLER_RST_DEVICES_X_0, SWR_SOR0_RST, 0)
// REG(CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0, CLK_ENB_SOR0, 1)
// REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0, 0) //0x60006414
setbits_le32(&clkrst->rst_devices_x, SWR_SOR0_RST); // Set Reset
clrbits_le32(&clkrst->rst_devices_x, SWR_SOR0_RST); // Clear Reset
setbits_le32(&clkrst->clk_out_enb_x, CLK_ENB_SOR0); // Set Enable
WRITEL(0x0, (void *)(0x60006000 + 0x414)); // CLK_SOURCE_SOR0 = PLLP
//WRITEL(0xc000c000, (0x60006000 + 0x414)); // CLK_SOURCE_SOR0 = CLK_M
#if 1
#define SOR_WRITE(reg, val) \
{ \
@ -410,137 +141,13 @@ void init_sor_regs(void)
WRITEL(_reg_val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \
}
SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE0_0, 0x00000000); //0x54540004
SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE1_0, 0x00000000); //0x54540008
SOR_WRITE(SOR_NV_PDISP_SOR_STATE0_0, 0x00000000); //0x5454000c
SOR_WRITE(SOR_NV_PDISP_SOR_STATE1_0, 0x00000040); //0x54540010
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE0, 0x00000000); //0x54540014
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE0_1, 0x00000000); //0x54540018
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE1, 0x01011000); //0x5454001c
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE1_1, 0x01011000); //0x54540020
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE2, 0x00000001); //0x54540024
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE2_1, 0x00000001); //0x54540028
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE3, 0x00010011); //0x5454002c
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE3_1, 0x00010011); //0x54540030
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE4, 0x00110100); //0x54540034
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE4_1, 0x00110100); //0x54540038
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE5, 0x00000001); //0x5454003c
SOR_WRITE(SOR_NV_PDISP_HEAD_STATE5_1, 0x00000001); //0x54540040
SOR_WRITE(SOR_NV_PDISP_SOR_CRC_CNTRL_0, 0x00000000); //0x54540044
SOR_WRITE(SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0, 0x00000000); //0x54540048
SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, 0x00000018); //0x5454004c
SOR_WRITE(SOR_NV_PDISP_SOR_CAP_0, 0x00000000); //0x54540050
SOR_WRITE(SOR_NV_PDISP_SOR_PWR_0, 0x00000000); //0x54540054
SOR_WRITE(SOR_NV_PDISP_SOR_TEST_0, 0x00800000); //0x54540058
SOR_WRITE(SOR_NV_PDISP_SOR_PLL0_0, 0x0f0003d5); //0x5454005c
SOR_WRITE(SOR_NV_PDISP_SOR_PLL1_0, 0x00001000); //0x54540060
SOR_WRITE(SOR_NV_PDISP_SOR_PLL2_0, 0x01c00000); //0x54540064
SOR_WRITE(SOR_NV_PDISP_SOR_PLL3_0, 0x38002220); //0x54540068
SOR_WRITE(SOR_NV_PDISP_SOR_CSTM_0, 0x0001c800); //0x5454006c
SOR_WRITE(SOR_NV_PDISP_SOR_LVDS_0, 0x0001c800); //0x54540070
SOR_WRITE(SOR_NV_PDISP_SOR_CRCA_0, 0x00000000); //0x54540074
SOR_WRITE(SOR_NV_PDISP_SOR_CRCB_0, 0x00000000); //0x54540078
SOR_WRITE(SOR_NV_PDISP_SOR_BLANK_0, 0x00000000); //0x5454007c
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_CTL_0, 0x00008800); //0x54540080
SOR_WRITE(SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0, 0x00011000); //0x54540084
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST0_0, 0x01008000); //0x54540088
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST1_0, 0x01008000); //0x5454008c
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST2_0, 0x01008000); //0x54540090
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST3_0, 0x01008000); //0x54540094
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST4_0, 0x01008000); //0x54540098
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST5_0, 0x01008000); //0x5454009c
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST6_0, 0x01008000); //0x545400a0
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST7_0, 0x01008000); //0x545400a4
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST8_0, 0x01008000); //0x545400a8
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST9_0, 0x01008000); //0x545400ac
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTA_0, 0x01008000); //0x545400b0
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTB_0, 0x01008000); //0x545400b4
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTC_0, 0x01008000); //0x545400b8
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTD_0, 0x01008000); //0x545400bc
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTE_0, 0x01008000); //0x545400c0
SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTF_0, 0x01008000); //0x545400c4
SOR_WRITE(SOR_NV_PDISP_SOR_PWM_DIV_0, 0x00000000); //0x545400c8
SOR_WRITE(SOR_NV_PDISP_SOR_PWM_CTL_0, 0x00000000); //0x545400cc
SOR_WRITE(SOR_NV_PDISP_SOR_VCRCA0_0, 0x00000000); //0x545400d0
SOR_WRITE(SOR_NV_PDISP_SOR_VCRCA1_0, 0x00000000); //0x545400d4
SOR_WRITE(SOR_NV_PDISP_SOR_VCRCB0_0, 0x00000000); //0x545400d8
SOR_WRITE(SOR_NV_PDISP_SOR_VCRCB1_0, 0x00000000); //0x545400dc
SOR_WRITE(SOR_NV_PDISP_SOR_CCRCA0_0, 0x00000000); //0x545400e0
SOR_WRITE(SOR_NV_PDISP_SOR_CCRCA1_0, 0x00000000); //0x545400e4
SOR_WRITE(SOR_NV_PDISP_SOR_CCRCB0_0, 0x00000000); //0x545400e8
SOR_WRITE(SOR_NV_PDISP_SOR_CCRCB1_0, 0x00000000); //0x545400ec
SOR_WRITE(SOR_NV_PDISP_SOR_EDATAA0_0, 0x00000000); //0x545400f0
SOR_WRITE(SOR_NV_PDISP_SOR_EDATAA1_0, 0x00000000); //0x545400f4
SOR_WRITE(SOR_NV_PDISP_SOR_EDATAB0_0, 0x00000000); //0x545400f8
SOR_WRITE(SOR_NV_PDISP_SOR_EDATAB1_0, 0x00000000); //0x545400fc
SOR_WRITE(SOR_NV_PDISP_SOR_COUNTA0_0, 0x00000000); //0x54540100
SOR_WRITE(SOR_NV_PDISP_SOR_COUNTA1_0, 0x00000000); //0x54540104
SOR_WRITE(SOR_NV_PDISP_SOR_COUNTB0_0, 0x00000000); //0x54540108
SOR_WRITE(SOR_NV_PDISP_SOR_COUNTB1_0, 0x00000000); //0x5454010c
SOR_WRITE(SOR_NV_PDISP_SOR_DEBUGA0_0, 0x00000000); //0x54540110
SOR_WRITE(SOR_NV_PDISP_SOR_DEBUGA1_0, 0x00000000); //0x54540114
SOR_WRITE(SOR_NV_PDISP_SOR_DEBUGB0_0, 0x00000000); //0x54540118
SOR_WRITE(SOR_NV_PDISP_SOR_DEBUGB1_0, 0x00000000); //0x5454011c
SOR_WRITE(SOR_NV_PDISP_SOR_TRIG_0, 0x00000000); //0x54540120
SOR_WRITE(SOR_NV_PDISP_SOR_MSCHECK_0, 0x80000000); //0x54540124
SOR_WRITE(SOR_NV_PDISP_SOR_XBAR_CTRL_0, 0x8d111a23); //0x54540128
SOR_WRITE(SOR_NV_PDISP_SOR_XBAR_POL_0, 0x00000000); //0x5454012c
SOR_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL0_0, 0x00000100); //0x54540130
SOR_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL1_0, 0x00000100); //0x54540134
SOR_WRITE(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0, 0x40404040); //0x54540138
SOR_WRITE(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0, 0x80808080); //0x5454013c
SOR_WRITE(SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0, 0x00000040); //0x54540140
SOR_WRITE(SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0, 0x00000080); //0x54540144
SOR_WRITE(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0, 0x00000000); //0x54540148
SOR_WRITE(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0, 0x00000000); //0x5454014c
SOR_WRITE(SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0, 0x00000000); //0x54540150
SOR_WRITE(SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0, 0x00000000); //0x54540154
SOR_WRITE(SOR_NV_PDISP_SOR_POSTCURSOR0_0, 0x00000000); //0x54540158
SOR_WRITE(SOR_NV_PDISP_SOR_POSTCURSOR1_0, 0x00000000); //0x5454015c
SOR_WRITE(SOR_NV_PDISP_SOR_DP_CONFIG0_0, 0x94000000); //0x54540160
SOR_WRITE(SOR_NV_PDISP_SOR_DP_CONFIG1_0, 0x94000000); //0x54540164
SOR_WRITE(SOR_NV_PDISP_SOR_DP_MN0_0, 0x00008000); //0x54540168
SOR_WRITE(SOR_NV_PDISP_SOR_DP_MN1_0, 0x00008000); //0x5454016c
SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, 0x00800000); //0x54540170
SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL1_0, 0x00000000); //0x54540174
SOR_WRITE(SOR_NV_PDISP_SOR_DP_DEBUG0_0, 0x00000000); //0x54540178
SOR_WRITE(SOR_NV_PDISP_SOR_DP_DEBUG1_0, 0x00000000); //0x5454017c
SOR_WRITE(SOR_NV_PDISP_SOR_DP_SPARE0_0, 0x00000002); //0x54540180
SOR_WRITE(SOR_NV_PDISP_SOR_DP_SPARE1_0, 0x00000000); //0x54540184
SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0, 0x001f0001); //0x54540188
SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0, 0x00000000); //0x5454018c
SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0, 0x00000000); //0x54540190
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0, 0x00000000); //0x54540194
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0,0x00000000); //0x54540198
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0,0x00000000); //0x5454019c
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0,0x00000000); //0x545401a0
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0,0x00000000); //0x545401a4
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0,0x00000000); //0x545401a8
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0,0x00000000); //0x545401ac
SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0,0x00000000); //0x545401b0
SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_0, 0x50505050); //0x545401b4
SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0, 0x00000000); //0x545401b8
SOR_WRITE(SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0, 0x00000000); //0x545401bc
SOR_WRITE(SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0, 0x00000000); //0x545401c0
SOR_WRITE(SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0, 0x00000000); //0x545401c4
printk(BIOS_SPEW, "initial SOR done\n");
}
void init_dpaux_regs(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE;
// u32 val;
printk(BIOS_SPEW, "JZ: %s: entry\n", __func__);
#define SWR_DPAUX_RST (1 << 21)
#define CLK_ENB_DPAUX SWR_DPAUX_RST
// REG(CLK_RST_CONTROLLER_RST_DEVICES_X_0, SWR_DPAUX_RST, 1)
// REG(CLK_RST_CONTROLLER_RST_DEVICES_X_0, SWR_DPAUX_RST, 0)
// REG(CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0, CLK_ENB_DPAUX, 1)
setbits_le32(&clkrst->rst_devices_x, SWR_DPAUX_RST); // Set Reset
clrbits_le32(&clkrst->rst_devices_x, SWR_DPAUX_RST); // Clear Reset
setbits_le32(&clkrst->clk_out_enb_x, CLK_ENB_DPAUX); // Set Enable
printk(BIOS_SPEW, "%s: entry\n", __func__);
#if 1
#define DPAUX_WRITE(reg, val) \
@ -560,29 +167,6 @@ void init_dpaux_regs(void)
}
#endif
DPAUX_WRITE(DPAUX_INTR_EN_AUX, 0x00000000); //0x545c0004
DPAUX_WRITE(DPAUX_INTR_AUX, 0x00000000); //0x545c0014
DPAUX_WRITE(DPAUX_DP_AUXDATA_WRITE_W0, 0x00000000); //0x545c0024
DPAUX_WRITE(DPAUX_DP_AUXDATA_WRITE_W1, 0x00000000); //0x545c0034
DPAUX_WRITE(DPAUX_DP_AUXDATA_WRITE_W2, 0x00000000); //0x545c0044
DPAUX_WRITE(DPAUX_DP_AUXDATA_WRITE_W3, 0x00000000); //0x545c0054
DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W0, 0x00000000); //0x545c0064
DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W1, 0x00000000); //0x545c0074
DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W2, 0x00000000); //0x545c0084
DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W3, 0x00000000); //0x545c0094
DPAUX_WRITE(DPAUX_DP_AUXADDR, 0x00000000); //0x545c00a4
DPAUX_WRITE(DPAUX_DP_AUXCTL, 0x00000000); //0x545c00b4
DPAUX_WRITE(DPAUX_DP_AUXSTAT, 0x10000000); //0x545c00c4
DPAUX_WRITE(DPAUX_DP_AUX_SINKSTATLO, 0x00000000); //0x545c00d4
DPAUX_WRITE(DPAUX_DP_AUX_SINKSTATHI, 0x00000000); //0x545c00e4
DPAUX_WRITE(DPAUX_HPD_CONFIG, 0x07d000fa); //0x545c00f4
DPAUX_WRITE(DPAUX_HPD_IRQ_CONFIG, 0x000000fa); //0x545c0104
DPAUX_WRITE(DPAUX_DP_AUX_CONFIG, 0x00000190); //0x545c0114
DPAUX_WRITE(DPAUX_HYBRID_PADCTL, 0x00002462); //0x545c0124
DPAUX_WRITE(DPAUX_HYBRID_SPARE, 0x00000000); //0x545c0134
DPAUX_WRITE(DPAUX_SCRATCH_REG0_0, 0x00000000); //0x545c0144
DPAUX_WRITE(DPAUX_SCRATCH_REG1_0, 0x00000000); //0x545c0154
DPAUX_WRITE(DPAUX_SCRATCH_REG2_0, 0x00000000); //0x545c0164
printk(BIOS_SPEW, "initial DPAUX done\n");
}
@ -634,48 +218,8 @@ static void dp_io_set_dpd(u32 power_down)
void dp_io_powerup(void)
{
//E_DPD = PMC.dpd2_status[25]
//PDBG = SOR_NV_PDISP_SOR_PLL2_0.AUX6(1) | SEQ.POWERDOWN_MACRO(1) &
//SOR_NV_PDISP_SOR_PLL2_0.AUX2(0)
//PDPLL = SOR_NV_PDISP_SOR_PLL0_0.PWR(1) | SEQ.PDPLL(0) & ~ SOR_NV_PDISP_SOR_PLL2_0.AUX1(0)
//VCOPD = SOR_NV_PDISP_SOR_PLL0_0.VCOPD(1)
//CAPPD = SOR_NV_PDISP_SOR_PLL2_0.AUX8(1) | SEQ.ASSERT_PLL_RESET(0) &
//~ SOR_NV_PDISP_SOR_PLL2_0.AUX1(0)
//PDPORT = SOR_NV_PDISP_SOR_PLL2_0.AUX7(1) | SEQ.PDPORT(1) &
//~ SOR_NV_PDISP_SOR_DP_LINKCTL0_0.ENABLE(0)
//PDCAL = SOR_NV_PDISP_SOR_DP_PADCTL0_0.PAD_CAL_PD(1)
// struct clk_rst_ctlr *clkrst =
// (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE;
u32 reg_val;
printk(BIOS_SPEW, "%s: entry\n", __func__);
#if 0
printk(BIOS_SPEW, "JZ: %s: %d: do nothing, ret\n", __func__, __LINE__);
return;
#endif
#define SOR0_CLK_SEL0 (1 << 14)
#define SOR0_CLK_SEL1 (1 << 15)
// REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0, SOR0_CLK_SEL1, 0);
// REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0, SOR0_CLK_SEL0, 0);//sor safe clock
reg_val = READL((void *)(0x60006000 + 0x414));
reg_val &= ~(SOR0_CLK_SEL0 | SOR0_CLK_SEL1);
WRITEL(reg_val, (void *)(0x60006000 + 0x414));
// clock(PLLDP, 270)
WRITEL(0, (void *)(0x60006000 + 0x594)); // plldp_misc
WRITEL(0x11400000, (void *)(0x60006000 + 0x598)); // plldp_ss_cfg
WRITEL(0x80305a01, (void *)(0x60006000 + 0x590));// plldp_base, 12 * 90 / 4 = 270
WRITEL(0x11400000, (void *)(0x60006000 + 0x598)); // plldp_ss_cfg
WRITEL(0x40000000, (void *)(0x60006000 + 0x594)); // misc: enable lock
WRITEL(0xc0305a01, (void *)(0x60006000 + 0x590)); // base: enable
WRITEL(0xd8305a01, (void *)(0x60006000 + 0x590)); // base: check lock
WRITEL(0x58305a01, (void *)(0x60006000 + 0x590)); // base: disable bypass
WRITEL(0x11000000, (void *)(0x60006000 + 0x598)); // release clamp
udelay(10); // wait for plldp ready
SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, (6 << 2) | 2);//select PLLDP, lowest speed(6x)
SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, 0x00800000); //set PDCAL
SOR_WRITE(SOR_NV_PDISP_SOR_PLL0_0, 0x050003D5); //set PWR,VCOPD
@ -683,7 +227,6 @@ void dp_io_powerup(void)
SOR_WRITE(SOR_NV_PDISP_SOR_PLL2_0, 0x01C20000); //set AUX1,6,7,8; clr AUX2
SOR_WRITE(SOR_NV_PDISP_SOR_PLL3_0, 0x38002220);
//REG(SOR_NV_PDISP_SOR_PLL3_0,PLLVDD_MODE, V1_8)
dp_io_set_dpd(0);
udelay(1); //Deassert E_DPD to enable core logic circuits, and wait for > 5us
@ -728,8 +271,6 @@ static int dpaux_check(u32 bytes, u32 data, u32 mask)
printk(BIOS_SPEW, "******AuxRead Error:%04x: status %08x\n", 0x202,
status);
else {
//temp = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0] ;
//memcpy(&temp, buf, 4);
temp = DPAUX_READ(DPAUX_DP_AUXDATA_READ_W0);
if ((temp & mask) != (data & mask)) {
printk(BIOS_SPEW, "AuxCheck ERROR:(r_data) %08x & (mask) %08x != "
@ -803,7 +344,6 @@ static int dp_training(u32 level, u32 check, u32 speed)
u32 cnt = 0;
u32 cfg, cfg_d = 0;
u32 wcfg;
// u32 status = 0;
u8 buf[16];
while (cnt <= 5) {
@ -888,11 +428,7 @@ void dp_link_training(u32 lanes, u32 speed)
SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, ((speed << 2) | 2));
udelay(100);
//REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0,SOR0_CLK_SEL0, 1) //sor clk=pad macro output
reg_val = readl((void *)(0x60006000 + 0x414));
reg_val |= SOR0_CLK_SEL0;
writel(reg_val, (void *)(0x60006000 + 0x414));
sor_clock_start();
SOR_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL0_0,
(((0xF >> (4 - lanes)) << 16) | 1));
@ -907,10 +443,6 @@ void dp_link_training(u32 lanes, u32 speed)
printk(BIOS_SPEW, "set link rate and lane number: %dMHz, %d lanes\n",
(speed * 27), lanes);
// printk(BIOS_SPEW,"JZ: dbg ret\n");
// return;
// %d = (%lanes<<8) | %speed
dpaux_write(0x100, 2, ((lanes << 8) | speed));
printk(BIOS_SPEW, "precharge lane 10us\n");
reg_val = SOR_READ(SOR_NV_PDISP_SOR_DP_PADCTL0_0);
@ -963,7 +495,6 @@ static u32 div_f(u32 a, u32 b, u32 one)
u32 dp_setup_timing(u32 panel_id, u32 width, u32 height);
u32 dp_setup_timing(u32 panel_id, u32 width, u32 height)
{
u32 reg_val;
u32 pclk_freq = 0;
///////////////////////////////////////////
@ -978,11 +509,11 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height)
// 720x480: 27.00 , 594/22, dp CEA
// 640x480: 23.75 , 475/20, dp VESA
u32 PLL_FREQ = 570;
u32 PLL_FREQ = (12 / 12 * 283) / 1 / 2; /* 141.5 */
u32 PLL_DIV = 2;
u32 SYNC_WIDTH = (10 << 16) | 32;
u32 BACK_PORCH = (36 << 16) | 80;
u32 FRONT_PORCH = (3 << 16) | 48;
u32 SYNC_WIDTH = (8 << 16) | 46;
u32 BACK_PORCH = (6 << 16) | 44;
u32 FRONT_PORCH = (6 << 16) | 44;
u32 HSYNC_NEG = 1;
u32 VSYNC_NEG = 1;
@ -1006,27 +537,6 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height)
return pclk_freq;
}
// clock(plld2, %PLL_FREQ) // PLL_FREQ = 570
writel(0, (void *)(0x60006000 + 0x4bc)); // plld2_misc
writel(0x13400000, (void *)(0x60006000 + 0x570)); // plld2_ss_cfg
writel(0x8008010c, (void *)(0x60006000 + 0x4b8)); // plld2_base
writel(0x80105F01, (void *)(0x60006000 + 0x4b8));// plld2_base: 12 * 95 / 2 = 570
writel(0x40000000, (void *)(0x60006000 + 0x4bc)); // misc: enable lock
writel(0x80105f01, (void *)(0x60006000 + 0x4b8)); // base: enable
writel(0xc0105f01, (void *)(0x60006000 + 0x4b8)); // base: check lock
writel(0x58105f01, (void *)(0x60006000 + 0x4b8)); // base: disable bypass
writel(0x13800000, (void *)(0x60006000 + 0x570)); // plld2_ss_cfg
udelay(10); // wait for plld2 ready
// REG(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0, DISP1_CLK_SRC, PLLD2_OUT0)
#define DISP1_CLK_SRC (0x7 << 29)
#define PLLD2_OUT0 (0x5 << 29)
reg_val = readl((void *)(0x60006000 + 0x138));
reg_val &= ~DISP1_CLK_SRC;
reg_val |= PLLD2_OUT0;
writel(reg_val, (void *)(0x60006000 + 0x138));
udelay(10);
PLL_FREQ = PLL_FREQ * 1000000;
pclk_freq = PLL_FREQ / PLL_DIV;
PLL_FREQ_I = PLL_FREQ / 1000000;

View File

@ -73,7 +73,7 @@ int dma_busy(struct apb_dma_channel * const channel)
* as the channel is enabled. So for this function we'll use the
* DMA_ACTIVITY bit.
*/
return read32(&channel->regs->sta) & APBDMACHAN_STA_DMA_ACTIVITY ? 1 : 0;
return read32(&channel->regs->sta) & APB_STA_DMA_ACTIVITY ? 1 : 0;
}
/* claim a DMA channel */
struct apb_dma_channel * const dma_claim(void)
@ -85,7 +85,7 @@ struct apb_dma_channel * const dma_claim(void)
* Set global enable bit, otherwise register access to channel
* DMA registers will not be possible.
*/
setbits_le32(&apb_dma->command, APBDMA_COMMAND_GEN);
setbits_le32(&apb_dma->command, APB_COMMAND_GEN);
for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) {
regs = apb_dma_channels[i].regs;
@ -125,7 +125,7 @@ void dma_release(struct apb_dma_channel * const channel)
return;
}
clrbits_le32(&apb_dma->command, APBDMA_COMMAND_GEN);
clrbits_le32(&apb_dma->command, APB_COMMAND_GEN);
}
int dma_start(struct apb_dma_channel * const channel)
@ -133,7 +133,7 @@ int dma_start(struct apb_dma_channel * const channel)
struct apb_dma_channel_regs *regs = channel->regs;
/* Set ENB bit for this channel */
setbits_le32(&regs->csr, APBDMACHAN_CSR_ENB);
setbits_le32(&regs->csr, APB_CSR_ENB);
return 0;
}
@ -143,7 +143,7 @@ int dma_stop(struct apb_dma_channel * const channel)
struct apb_dma_channel_regs *regs = channel->regs;
/* Clear ENB bit for this channel */
clrbits_le32(&regs->csr, APBDMACHAN_CSR_ENB);
clrbits_le32(&regs->csr, APB_CSR_ENB);
return 0;
}

View File

@ -33,20 +33,20 @@
* bit controls or represents the status for the corresponding channel.
* So we will not bother to list each individual bit in this case.
*/
#define APBDMA_COMMAND_GEN (1 << 31)
#define APB_COMMAND_GEN (1 << 31)
#define APBDMA_CNTRL_REG_COUNT_VALUE_MASK 0xffff
#define APBDMA_CNTRL_REG_COUNT_VALUE_SHIFT 0
#define APB_CNTRL_REG_COUNT_VALUE_MASK 0xffff
#define APB_CNTRL_REG_COUNT_VALUE_SHIFT 0
/*
* Note: Many APB DMA controller registers are laid out such that each
* bit controls or represents the status for the corresponding channel.
* So we will not bother to list each individual bit in this case.
*/
#define APBDMA_COMMAND_GEN (1 << 31)
#define APB_COMMAND_GEN (1 << 31)
#define APBDMA_CNTRL_REG_COUNT_VALUE_MASK 0xffff
#define APBDMA_CNTRL_REG_COUNT_VALUE_SHIFT 0
#define APB_CNTRL_REG_COUNT_VALUE_MASK 0xffff
#define APB_CNTRL_REG_COUNT_VALUE_SHIFT 0
struct apb_dma {
u32 command; /* 0x00 */
u32 status; /* 0x04 */
@ -75,14 +75,14 @@ struct apb_dma {
* Naming in the doc included a superfluous _CHANNEL_n_ for
* each entry and was left out for the sake of conciseness.
*/
#define APBDMACHAN_CSR_ENB (1 << 31)
#define APBDMACHAN_CSR_IE_EOC (1 << 30)
#define APBDMACHAN_CSR_HOLD (1 << 29)
#define APBDMACHAN_CSR_DIR (1 << 28)
#define APBDMACHAN_CSR_ONCE (1 << 27)
#define APBDMACHAN_CSR_FLOW (1 << 21)
#define APBDMACHAN_CSR_REQ_SEL_MASK 0x1f
#define APBDMACHAN_CSR_REQ_SEL_SHIFT 16
#define APB_CSR_ENB (1 << 31)
#define APB_CSR_IE_EOC (1 << 30)
#define APB_CSR_HOLD (1 << 29)
#define APB_CSR_DIR (1 << 28)
#define APB_CSR_ONCE (1 << 27)
#define APB_CSR_FLOW (1 << 21)
#define APB_CSR_REQ_SEL_MASK 0x1f
#define APB_CSR_REQ_SEL_SHIFT 16
enum apbdmachan_req_sel {
APBDMA_SLAVE_CNTR_REQ = 0,
@ -119,46 +119,41 @@ enum apbdmachan_req_sel {
APBDMA_SLAVE_NA31 = 31,
};
#define APBDMACHAN_STA_BSY (1 << 31)
#define APBDMACHAN_STA_ISE_EOC (1 << 30)
#define APBDMACHAN_STA_HALT (1 << 29)
#define APBDMACHAN_STA_PING_PONG_STA (1 << 28)
#define APBDMACHAN_STA_DMA_ACTIVITY (1 << 27)
#define APBDMACHAN_STA_CHANNEL_PAUSE (1 << 26)
#define APB_STA_BSY (1 << 31)
#define APB_STA_ISE_EOC (1 << 30)
#define APB_STA_HALT (1 << 29)
#define APB_STA_PING_PONG_STA (1 << 28)
#define APB_STA_DMA_ACTIVITY (1 << 27)
#define APB_STA_CHANNEL_PAUSE (1 << 26)
#define APBDMACHAN_CSRE_CHANNEL_PAUSE (1 << 31)
#define APBDMACHAN_CSRE_TRIG_SEL_MASK 0x3f
#define APBDMACHAN_CSRE_TRIG_SEL_SHIFT 14
#define APB_CSRE_CHANNEL_PAUSE (1 << 31)
#define APB_CSRE_TRIG_SEL_MASK 0x3f
#define APB_CSRE_TRIG_SEL_SHIFT 14
#define APBDMACHAN_AHB_PTR_MASK (0x3fffffff)
#define APBDMACHAN_AHB_PTR_SHIFT 2
#define AHB_PTR_MASK (0x3fffffff)
#define AHB_PTR_SHIFT 2
#define APBDMACHAN_AHB_SEQ_INTR_ENB (1 << 31)
#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7
#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28
#define APBDMACHAN_AHB_SEQ_AHB_DATA_SWAP (1 << 27)
#define APBDMACHAN_AHB_SEQ_AHB_BURST_MASK 0x7
#define APBDMACHAN_AHB_SEQ_AHB_BURST_SHIFT 24
#define APBDMACHAN_AHB_SEQ_DBL_BUF (1 << 19)
#define APBDMACHAN_AHB_SEQ_WRAP_MASK 0x7
#define APBDMACHAN_AHB_SEQ_WRAP_SHIFT 16
#define AHB_SEQ_INTR_ENB (1 << 31)
#define AHB_BUS_WIDTH_MASK 0x7
#define AHB_BUS_WIDTH_SHIFT 28
#define AHB_DATA_SWAP (1 << 27)
#define AHB_BURST_MASK 0x7
#define AHB_BURST_SHIFT 24
#define AHB_SEQ_DBL_BUF (1 << 19)
#define AHB_SEQ_WRAP_MASK 0x7
#define AHB_SEQ_WRAP_SHIFT 16
#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7
#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28
#define APB_PTR_MASK 0x3fffffff
#define APB_PTR_SHIFT 2
#define APBDMACHAN_APB_PTR_MASK 0x3fffffff
#define APBDMACHAN_APB_PTR_SHIFT 2
#define APB_BUS_WIDTH_MASK 0x7
#define APB_BUS_WIDTH_SHIFT 28
#define APB_DATA_SWAP (1 << 27)
#define APB_ADDR_WRAP_MASK 0x7
#define APB_ADDR_WRAP_SHIFT 16
#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_MASK 0x7
#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_SHIFT 28
#define APBDMACHAN_APB_SEQ_APB_DATA_SWAP (1 << 27)
#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_MASK 0x7
#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_SHIFT 16
#define APBDMACHAN_WORD_TRANSFER_
#define APBDMACHAN_WORD_TRANSFER_MASK 0x0fffffff
#define APBDMACHAN_WORD_TRANSFER_SHIFT 2
#define APB_WORD_TRANSFER_MASK 0x0fffffff
#define APB_WORD_TRANSFER_SHIFT 2
struct apb_dma_channel_regs {
u32 csr; /* 0x00 */

View File

@ -22,90 +22,88 @@
#include <string.h>
#include <delay.h>
#include <soc/addressmap.h>
#include "i2c.h"
#include "dc.h"
/* shit. This is broken. */
#include <soc/nvidia/tegra124/sor.h>
// this is really broken. #include <soc/ardpaux.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra/dc.h>
#include "sor.h"
#include <soc/nvidia/tegra/displayport.h>
extern int dump;
unsigned long READL(void* p);
void WRITEL(unsigned long value, void* p);
unsigned long READL(void *p);
void WRITEL(unsigned long value, void *p);
static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
{
void *addr = dp->aux_base + (u32)(reg <<2);
void *addr = dp->aux_base + (u32) (reg << 2);
u32 reg_val = READL(addr);
return reg_val;
}
static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
u32 reg, u32 val)
u32 reg, u32 val)
{
void *addr = dp->aux_base + (u32)(reg <<2);
void *addr = dp->aux_base + (u32) (reg << 2);
WRITEL(val, addr);
}
static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
u32 reg, u32 mask, u32 exp_val,
u32 poll_interval_us,
u32 timeout_ms)
{
// unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
u32 reg_val = 0;
u32 reg_val = 0;
printk(BIOS_SPEW, "JZ: %s: enter, poll_reg: %#x: timeout: 0x%x\n",
__func__, reg*4, timeout_ms);
__func__, reg * 4, timeout_ms);
do {
// udelay(poll_interval_us);
udelay(1);
reg_val = tegra_dpaux_readl(dp, reg);
} while (((reg_val & mask) != exp_val) && (--timeout_ms > 0));
if ((reg_val & mask) == exp_val)
return 0; /* success */
printk(BIOS_SPEW,"dpaux_poll_register 0x%x: timeout: (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", reg, reg_val, mask, exp_val);
printk(BIOS_SPEW,
"dpaux_poll_register 0x%x: timeout: "
"(reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
reg, reg_val, mask, exp_val);
return timeout_ms;
}
static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
{
/* According to DP spec, each aux transaction needs to finish
within 40ms. */
if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL,
DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
100, DP_AUX_TIMEOUT_MS*1000) != 0) {
printk(BIOS_SPEW,"dp: DPAUX transaction timeout\n");
DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
100, DP_AUX_TIMEOUT_MS * 1000) != 0) {
printk(BIOS_SPEW, "dp: DPAUX transaction timeout\n");
return -1;
}
return 0;
}
static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
u32 addr, u8 *data, u32 *size, u32 *aux_stat)
u32 addr, u8 * data, u32 * size,
u32 * aux_stat)
{
int i;
u32 reg_val;
u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
u32 defer_retries = DP_AUX_DEFER_MAX_TRIES;
u32 temp_data;
int i;
u32 reg_val;
u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
u32 defer_retries = DP_AUX_DEFER_MAX_TRIES;
u32 temp_data;
if (*size > DP_AUX_MAX_BYTES)
return -1; /* only write one chunk of data */
/* Make sure the command is write command */
switch (cmd) {
case DPAUX_DP_AUXCTL_CMD_I2CWR:
case DPAUX_DP_AUXCTL_CMD_MOTWR:
case DPAUX_DP_AUXCTL_CMD_AUXWR:
break;
default:
printk(BIOS_SPEW,"dp: aux write cmd 0x%x is invalid\n",
cmd);
return -1;
case DPAUX_DP_AUXCTL_CMD_I2CWR:
case DPAUX_DP_AUXCTL_CMD_MOTWR:
case DPAUX_DP_AUXCTL_CMD_AUXWR:
break;
default:
printk(BIOS_SPEW, "dp: aux write cmd 0x%x is invalid\n", cmd);
return -1;
}
#if 0
@ -113,17 +111,16 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
if (tegra_platform_is_silicon()) {
*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
printk(BIOS_SPEW,"dp: HPD is not detected\n");
printk(BIOS_SPEW, "dp: HPD is not detected\n");
return -EFAULT;
}
}
#endif
tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i) {
for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) {
memcpy(&temp_data, data, 4);
tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i),
temp_data);
tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), temp_data);
data += 4;
}
@ -131,18 +128,18 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
reg_val |= cmd;
reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
reg_val |= ((*size-1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
while ((timeout_retries > 0) && (defer_retries > 0)) {
if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
(defer_retries != DP_AUX_DEFER_MAX_TRIES))
(defer_retries != DP_AUX_DEFER_MAX_TRIES))
udelay(1);
reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
if (tegra_dpaux_wait_transaction(dp))
printk(BIOS_SPEW,"dp: aux write transaction timeout\n");
printk(BIOS_SPEW, "dp: aux write transaction timeout\n");
*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
@ -151,15 +148,14 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
(*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
(*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
if (timeout_retries-- > 0) {
printk(BIOS_SPEW,"dp: aux write retry (0x%x) -- %d\n",
*aux_stat, timeout_retries);
printk(BIOS_SPEW, "dp: aux write retry (0x%x) -- %d\n",
*aux_stat, timeout_retries);
/* clear the error bits */
tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
*aux_stat);
tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat);
continue;
} else {
printk(BIOS_SPEW,"dp: aux write got error (0x%x)\n",
*aux_stat);
printk(BIOS_SPEW, "dp: aux write got error (0x%x)\n",
*aux_stat);
return -1;
}
}
@ -168,15 +164,13 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
(*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
if (defer_retries-- > 0) {
printk(BIOS_SPEW, "dp: aux write defer (0x%x) -- %d\n",
*aux_stat, defer_retries);
*aux_stat, defer_retries);
/* clear the error bits */
tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
*aux_stat);
tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat);
continue;
} else {
printk(BIOS_SPEW, "dp: aux write defer exceeds max retries "
"(0x%x)\n",
*aux_stat);
"(0x%x)\n", *aux_stat);
return -1;
}
}
@ -186,7 +180,7 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
*size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
return 0;
} else {
printk(BIOS_SPEW,"dp: aux write failed (0x%x)\n", *aux_stat);
printk(BIOS_SPEW, "dp: aux write failed (0x%x)\n", *aux_stat);
return -1;
}
}
@ -195,12 +189,12 @@ static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
}
static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
u8 *data, u32 *size, u32 *aux_stat)
u8 * data, u32 * size, u32 * aux_stat)
{
u32 cur_size = 0;
u32 finished = 0;
u32 cur_left;
int ret = 0;
u32 cur_size = 0;
u32 finished = 0;
u32 cur_left;
int ret = 0;
do {
cur_size = *size - finished;
@ -208,7 +202,7 @@ static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
cur_size = DP_AUX_MAX_BYTES;
cur_left = cur_size;
ret = tegra_dc_dpaux_write_chunk(dp, cmd, addr,
data, &cur_left, aux_stat);
data, &cur_left, aux_stat);
cur_size -= cur_left;
finished += cur_size;
@ -224,31 +218,32 @@ static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
}
static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
u32 addr, u8 *data, u32 *size, u32 *aux_stat)
u32 addr, u8 * data, u32 * size,
u32 * aux_stat)
{
u32 reg_val;
u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
u32 defer_retries = DP_AUX_DEFER_MAX_TRIES;
u32 reg_val;
u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
u32 defer_retries = DP_AUX_DEFER_MAX_TRIES;
if (*size > DP_AUX_MAX_BYTES)
return -1; /* only read one chunk */
/* Check to make sure the command is read command */
switch (cmd) {
case DPAUX_DP_AUXCTL_CMD_I2CRD:
case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
case DPAUX_DP_AUXCTL_CMD_MOTRD:
case DPAUX_DP_AUXCTL_CMD_AUXRD:
break;
default:
printk(BIOS_SPEW,"dp: aux read cmd 0x%x is invalid\n", cmd);
return -1;
case DPAUX_DP_AUXCTL_CMD_I2CRD:
case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
case DPAUX_DP_AUXCTL_CMD_MOTRD:
case DPAUX_DP_AUXCTL_CMD_AUXRD:
break;
default:
printk(BIOS_SPEW, "dp: aux read cmd 0x%x is invalid\n", cmd);
return -1;
}
if (0){
if (0) {
*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
printk(BIOS_SPEW,"dp: HPD is not detected\n");
printk(BIOS_SPEW, "dp: HPD is not detected\n");
//return EFAULT;
}
}
@ -260,11 +255,11 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
reg_val |= cmd;
printk(BIOS_SPEW, "cmd = %08x\n", reg_val);
reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
reg_val |= ((*size-1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
printk(BIOS_SPEW, "cmd = %08x\n", reg_val);
while ((timeout_retries > 0) && (defer_retries > 0)) {
if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
(defer_retries != DP_AUX_DEFER_MAX_TRIES))
(defer_retries != DP_AUX_DEFER_MAX_TRIES))
udelay(DP_DPCP_RETRY_SLEEP_NS * 2);
reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
@ -272,7 +267,7 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
if (tegra_dpaux_wait_transaction(dp))
printk(BIOS_SPEW,"dp: aux read transaction timeout\n");
printk(BIOS_SPEW, "dp: aux read transaction timeout\n");
*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
printk(BIOS_SPEW, "dp: %s: aux stat: 0x%08x\n", __func__, *aux_stat);
@ -283,14 +278,12 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
(*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
if (timeout_retries-- > 0) {
printk(BIOS_SPEW, "dp: aux read retry (0x%x) -- %d\n",
*aux_stat, timeout_retries);
*aux_stat, timeout_retries);
/* clear the error bits */
tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
*aux_stat);
continue; /* retry */
tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat);
continue; /* retry */
} else {
printk(BIOS_SPEW,"dp: aux read got error (0x%x)\n",
*aux_stat);
printk(BIOS_SPEW, "dp: aux read got error (0x%x)\n", *aux_stat);
return -1;
}
}
@ -299,14 +292,13 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
(*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
if (defer_retries-- > 0) {
printk(BIOS_SPEW, "dp: aux read defer (0x%x) -- %d\n",
*aux_stat, defer_retries);
*aux_stat, defer_retries);
/* clear the error bits */
tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
*aux_stat);
tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, *aux_stat);
continue;
} else {
printk(BIOS_SPEW,"dp: aux read defer exceeds max retries "
"(0x%x)\n", *aux_stat);
printk(BIOS_SPEW, "dp: aux read defer exceeds max retries "
"(0x%x)\n", *aux_stat);
return -1;
}
}
@ -316,9 +308,9 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
int i;
u32 temp_data[4];
for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i)
for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i)
temp_data[i] = tegra_dpaux_readl(dp,
DPAUX_DP_AUXDATA_READ_W(i));
DPAUX_DP_AUXDATA_READ_W(i));
*size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
printk(BIOS_SPEW, "dp: aux read data %d bytes\n", *size);
@ -326,7 +318,7 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
return 0;
} else {
printk(BIOS_SPEW,"dp: aux read failed (0x%x\n", *aux_stat);
printk(BIOS_SPEW, "dp: aux read failed (0x%x\n", *aux_stat);
return -1;
}
}
@ -336,11 +328,11 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
}
int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
u8 *data, u32 *size, u32 *aux_stat)
u8 * data, u32 * size, u32 * aux_stat)
{
u32 finished = 0;
u32 cur_size;
int ret = 0;
u32 finished = 0;
u32 cur_size;
int ret = 0;
do {
cur_size = *size - finished;
@ -348,7 +340,7 @@ int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
cur_size = DP_AUX_MAX_BYTES;
ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr,
data, &cur_size, aux_stat);
data, &cur_size, aux_stat);
/* cur_size should be the real size returned */
addr += cur_size;
@ -360,7 +352,7 @@ int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
#if 0
if (cur_size == 0) {
printk(BIOS_SPEW,"JZ: no data found, ret\n");
printk(BIOS_SPEW, "JZ: no data found, ret\n");
break;
}
#endif
@ -371,57 +363,56 @@ int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
}
static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
u8 *data_ptr)
u8 * data_ptr)
{
u32 size = 1;
u32 status = 0;
int ret;
ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
cmd, data_ptr, &size, &status);
cmd, data_ptr, &size, &status);
if (ret)
printk(BIOS_SPEW,"dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
cmd, status);
printk(BIOS_SPEW,
"dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n", cmd,
status);
return ret;
}
static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
struct tegra_dc_dp_link_config *cfg)
struct tegra_dc_dp_link_config *cfg)
{
u8 dpcd_data;
int ret;
u8 dpcd_data;
int ret;
ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT,
&dpcd_data);
ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT, &dpcd_data);
if (ret)
return ret;
cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
printk(BIOS_SPEW, "JZ: %s: max_lane_count: %d\n", __func__, cfg->max_lane_count);
printk(BIOS_SPEW, "JZ: %s: max_lane_count: %d\n", __func__,
cfg->max_lane_count);
cfg->support_enhanced_framing =
(dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
1 : 0;
printk(BIOS_SPEW, "JZ: %s: enh-framing: %d\n", __func__, cfg->support_enhanced_framing);
(dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ? 1 : 0;
printk(BIOS_SPEW, "JZ: %s: enh-framing: %d\n", __func__,
cfg->support_enhanced_framing);
ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
&dpcd_data);
ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD, &dpcd_data);
if (ret)
return ret;
cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
1 : 0;
cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ? 1 : 0;
printk(BIOS_SPEW, "JZ: %s: downspread: %d\n", __func__, cfg->downspread);
ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
&cfg->max_link_bw);
&cfg->max_link_bw);
if (ret)
return ret;
printk(BIOS_SPEW, "JZ: %s: max_link_bw: %d\n", __func__, cfg->max_link_bw);
// jz, changed
// cfg->bits_per_pixel = dp->dc->pdata->default_out->depth;
cfg->bits_per_pixel = 24;
cfg->bits_per_pixel = 18;
/* TODO: need to come from the board file */
/* Venice2 settings */
@ -429,32 +420,25 @@ static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
cfg->preemphasis = 0;
cfg->postcursor = 0;
ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
&dpcd_data);
ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP, &dpcd_data);
if (ret)
return ret;
cfg->alt_scramber_reset_cap =
(dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
1 : 0;
(dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ? 1 : 0;
cfg->only_enhanced_framing =
(dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
1 : 0;
printk(BIOS_SPEW, "JZ: %s: alt_reset_cap: %d, only_enh_framing: %d\n", __func__,
cfg->alt_scramber_reset_cap, cfg->only_enhanced_framing);
(dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ? 1 : 0;
printk(BIOS_SPEW, "JZ: %s: alt_reset_cap: %d, only_enh_framing: %d\n",
__func__, cfg->alt_scramber_reset_cap, cfg->only_enhanced_framing);
cfg->lane_count = cfg->max_lane_count;
cfg->link_bw = cfg->max_link_bw;
cfg->lane_count = cfg->max_lane_count;
cfg->link_bw = NV_SOR_LINK_SPEED_G1_62;
cfg->enhanced_framing = cfg->support_enhanced_framing;
return 0;
}
struct tegra_dc_dp_data dp_data;
//struct tegra_dc dc_data = {0};
struct tegra_dc_sor_data sor_data = {0};
struct tegra_dc_dp_data dp_data = {0};
static int tegra_dc_dpcd_read_rev(struct tegra_dc_dp_data *dp,
u8 *rev)
static int tegra_dc_dpcd_read_rev(struct tegra_dc_dp_data *dp, u8 * rev)
{
u32 size;
int ret;
@ -462,105 +446,101 @@ static int tegra_dc_dpcd_read_rev(struct tegra_dc_dp_data *dp,
size = 3;
ret = tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
NV_DPCD_REV, rev, &size, &status);
NV_DPCD_REV, rev, &size, &status);
if (ret) {
printk(BIOS_SPEW,"dp: Failed to read NV_DPCD_REV\n");
printk(BIOS_SPEW, "dp: Failed to read NV_DPCD_REV\n");
return ret;
}
return 0;
}
u32 dp_setup_timing(u32 panel_id, u32 width, u32 height);
void dp_bringup(u32 winb_addr)
{
struct tegra_dc_dp_data *dp = &dp_data;
struct tegra_dc_dp_data *dp = &dp_data;
u32 dpcd_rev;
u32 pclk_freq;
// int ret;
u32 dpcd_rev;
u32 pclk_freq;
printk(BIOS_SPEW, "JZ: %s: entry\n",__func__);
u32 xres = 1366; /* norrin display */
u32 yres = 768;
dp->sor = &sor_data;
// dp->sor->dc = dc;
dp->sor->base = (void *)TEGRA_ARM_SOR;
// dp->sor->base_res = base_res;
// dp->sor->sor_clk = clk;
dp->sor->link_cfg = &dp->link_cfg;
dp->sor->portnum = 0;
printk(BIOS_SPEW, "JZ: %s: entry\n", __func__);
dp->sor.base = (void *)TEGRA_ARM_SOR;
dp->sor.portnum = 0;
dp->aux_base = (void *)TEGRA_ARM_DPAUX;
/* dp->mode = 0; */ /* ???? */
/* read panel info */
if (!tegra_dc_dpcd_read_rev(dp, (u8 *)&dpcd_rev)) {
printk(BIOS_SPEW,"PANEL info: \n");
printk(BIOS_SPEW,"--DPCP version(%#x): %d.%d\n",
dpcd_rev, (dpcd_rev >> 4)&0x0f, (dpcd_rev & 0x0f));
if (!tegra_dc_dpcd_read_rev(dp, (u8 *) & dpcd_rev)) {
printk(BIOS_SPEW, "PANEL info: \n");
printk(BIOS_SPEW, "--DPCP version(%#x): %d.%d\n",
dpcd_rev, (dpcd_rev >> 4) & 0x0f, (dpcd_rev & 0x0f));
}
if (tegra_dc_dp_init_max_link_cfg(dp, &dp->link_cfg))
printk(BIOS_SPEW,"dp: failed to init link configuration\n");
printk(BIOS_SPEW, "dp: failed to init link configuration\n");
dp_link_training((u32)(dp->link_cfg.lane_count),
(u32)(dp->link_cfg.link_bw));
dp_link_training((u32) (dp->link_cfg.lane_count),
(u32) (dp->link_cfg.link_bw));
pclk_freq = dp_setup_timing(5, 2560, 1700); // W: 2560, H: 1700, use_plld2: 1
printk(BIOS_SPEW, "JZ: %s: pclk_freq: %d\n",__func__, pclk_freq);
pclk_freq = dp_setup_timing(5, xres, yres);
printk(BIOS_SPEW, "JZ: %s: pclk_freq: %d\n", __func__, pclk_freq);
// void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr)
void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
u32 lane_count, u32 enhanced_framing, u32 panel_edp,
u32 pclkfreq, u32 linkfreq);
void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
u32 lane_count, u32 enhanced_framing, u32 panel_edp,
u32 pclkfreq, u32 linkfreq);
dp_misc_setting(dp->link_cfg.bits_per_pixel,
2560, 1700, winb_addr,
(u32)dp->link_cfg.lane_count,
(u32)dp->link_cfg.enhanced_framing,
(u32)dp->link_cfg.alt_scramber_reset_cap,
pclk_freq,
dp->link_cfg.link_bw * 27);
xres, yres, winb_addr,
(u32) dp->link_cfg.lane_count,
(u32) dp->link_cfg.enhanced_framing,
(u32) dp->link_cfg.alt_scramber_reset_cap,
pclk_freq, dp->link_cfg.link_bw * 27);
}
void debug_dpaux_print(u32 addr, u32 size)
{
struct tegra_dc_dp_data *dp = &dp_data;
struct tegra_dc_dp_data *dp = &dp_data;
u32 status = 0;
u8 buf[16];
int i;
if ((size == 0) || (size > 16)) {
printk(BIOS_SPEW,"dp: %s: invalid size %d\n", __func__, size);
printk(BIOS_SPEW, "dp: %s: invalid size %d\n", __func__, size);
return;
}
if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
addr, buf, &size, &status)) {
printk(BIOS_SPEW,"******AuxRead Error: 0x%04x: status 0x%08x\n", addr, status);
addr, buf, &size, &status)) {
printk(BIOS_SPEW, "******AuxRead Error: 0x%04x: status 0x%08x\n", addr,
status);
return;
}
printk(BIOS_SPEW, "%s: addr: 0x%04x, size: %d\n", __func__, addr, size);
for (i=0; i < size; ++i)
printk(BIOS_SPEW," %02x", buf[i]);
for (i = 0; i < size; ++i)
printk(BIOS_SPEW, " %02x", buf[i]);
printk(BIOS_SPEW,"\n");
printk(BIOS_SPEW, "\n");
}
int dpaux_read(u32 addr, u32 size, u8 *data)
int dpaux_read(u32 addr, u32 size, u8 * data)
{
struct tegra_dc_dp_data *dp = &dp_data;
struct tegra_dc_dp_data *dp = &dp_data;
u32 status = 0;
if ((size == 0) || (size > 16)) {
printk(BIOS_SPEW,"dp: %s: invalid size %d\n", __func__, size);
printk(BIOS_SPEW, "dp: %s: invalid size %d\n", __func__, size);
return -1;
}
if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
addr, data, &size, &status)) {
printk(BIOS_SPEW,"dp: Failed to read reg %#x, status: %#x\n", addr, status);
addr, data, &size, &status)) {
printk(BIOS_SPEW, "dp: Failed to read reg %#x, status: %#x\n", addr,
status);
return -1;
}
@ -569,18 +549,17 @@ int dpaux_read(u32 addr, u32 size, u8 *data)
int dpaux_write(u32 addr, u32 size, u32 data)
{
struct tegra_dc_dp_data *dp = &dp_data;
struct tegra_dc_dp_data *dp = &dp_data;
u32 status = 0;
int ret;
printk(BIOS_SPEW, "JZ: %s: entry, addr: 0x%08x, size: 0x%08x, data: %#x\n",
__func__, addr, size, data);
__func__, addr, size, data);
ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
addr, (u8 *)&data, &size, &status);
addr, (u8 *) & data, &size, &status);
if (ret)
printk(BIOS_SPEW,"dp: Failed to write to reg %#x, status: 0x%x\n",
addr, status);
printk(BIOS_SPEW, "dp: Failed to write to reg %#x, status: 0x%x\n",
addr, status);
return ret;
}

View File

@ -37,13 +37,42 @@ struct flow_ctlr {
u32 ram_repair; /* offset 0x40 */
};
/* HALT_COP_EVENTS_0, 0x04 */
#define EVENT_MSEC (1 << 24)
#define EVENT_USEC (1 << 25)
#define EVENT_JTAG (1 << 28)
#define EVENT_MODE_STOP (2 << 29)
enum {
FLOW_MODE_SHIFT = 29,
FLOW_MODE_MASK = 0x7 << FLOW_MODE_SHIFT,
/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
#define ACTIVE_LP (1 << 0)
FLOW_MODE_NONE = 0 << FLOW_MODE_SHIFT,
FLOW_MODE_RUN_AND_INT = 1 << FLOW_MODE_SHIFT,
FLOW_MODE_WAITEVENT = 2 << FLOW_MODE_SHIFT,
FLOW_MODE_WAITEVENT_AND_INT = 3 << FLOW_MODE_SHIFT,
FLOW_MODE_STOP_UNTIL_IRQ = 4 << FLOW_MODE_SHIFT,
FLOW_MODE_STOP_UNTIL_IRQ_AND_INT = 5 << FLOW_MODE_SHIFT,
FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ = 6 << FLOW_MODE_SHIFT,
};
/* HALT_COP_EVENTS_0, 0x04 */
enum {
FLOW_EVENT_GIC_FIQ = 1 << 8,
FLOW_EVENT_GIC_IRQ = 1 << 9,
FLOW_EVENT_LIC_FIQ = 1 << 10,
FLOW_EVENT_LIC_IRQ = 1 << 11,
FLOW_EVENT_IBF = 1 << 12,
FLOW_EVENT_IBE = 1 << 13,
FLOW_EVENT_OBF = 1 << 14,
FLOW_EVENT_OBE = 1 << 15,
FLOW_EVENT_XRQ_A = 1 << 16,
FLOW_EVENT_XRQ_B = 1 << 17,
FLOW_EVENT_XRQ_C = 1 << 18,
FLOW_EVENT_XRQ_D = 1 << 19,
FLOW_EVENT_SMP30 = 1 << 20,
FLOW_EVENT_SMP31 = 1 << 21,
FLOW_EVENT_X_RDY = 1 << 22,
FLOW_EVENT_SEC = 1 << 23,
FLOW_EVENT_MSEC = 1 << 24,
FLOW_EVENT_USEC = 1 << 25,
FLOW_EVENT_X32K = 1 << 26,
FLOW_EVENT_SCLK = 1 << 27,
FLOW_EVENT_JTAG = 1 << 28
};
#endif /* _TEGRA124_FLOW_H_ */

View File

@ -68,6 +68,7 @@ enum {
TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400,
TEGRA_EMC_BASE = TEGRA_APB_MISC_BASE + 0xF400,
TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800,
TEGRA_MC_BASE = 0x70019000,
TEGRA_CSITE_BASE = 0x70040000,
TEGRA_SYSCTR0_BASE = 0x700F0000,
TEGRA_USBD_BASE = 0x7D000000,

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -129,6 +129,7 @@ enum {
CLK_V_HDA2CODEC_2X = 0x1 << 15,
CLK_V_ATOMICS = 0x1 << 16,
CLK_V_ACTMON = 0x1 << 23,
CLK_V_EXTPERIPH1 = 0x1 << 24,
CLK_V_SATA = 0x1 << 28,
CLK_V_HDA = 0x1 << 29,
@ -142,7 +143,28 @@ enum {
CLK_W_DVFS = 0x1 << 27,
CLK_W_XUSB_SS = 0x1 << 28,
CLK_W_MC1 = 0x1 << 30,
CLK_W_EMC1 = 0x1 << 31
CLK_W_EMC1 = 0x1 << 31,
CLK_X_AFC0 = 0x1 << 31,
CLK_X_AFC1 = 0x1 << 30,
CLK_X_AFC2 = 0x1 << 29,
CLK_X_AFC3 = 0x1 << 28,
CLK_X_AFC4 = 0x1 << 27,
CLK_X_AFC5 = 0x1 << 26,
CLK_X_AMX1 = 0x1 << 25,
CLK_X_GPU = 0x1 << 24,
CLK_X_SOR0 = 0x1 << 22,
CLK_X_DPAUX = 0x1 << 21,
CLK_X_ADX1 = 0x1 << 20,
CLK_X_VIC = 0x1 << 18,
CLK_X_CLK72MHZ = 0x1 << 17,
CLK_X_HDMI_AUDIO = 0x1 << 16,
CLK_X_EMC_DLL = 0x1 << 14,
CLK_X_VIM2_CLK = 0x1 << 11,
CLK_X_I2C6 = 0x1 << 6,
CLK_X_CAM_MCLK2 = 0x1 << 5,
CLK_X_CAM_MCLK = 0x1 << 4,
CLK_X_SPARE = 0x1 << 0,
};
/* PLL stabilization delay in usec */
@ -191,12 +213,16 @@ enum {
*/
#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
#define clock_configure_irregular_source(device, src, freq, src_id) \
clrsetbits_le32(&clk_rst->clk_src_##device, \
CLK_SOURCE_MASK | CLK_DIVISOR_MASK, \
src_id << CLK_SOURCE_SHIFT | \
CLK_DIVIDER(TEGRA_##src##_KHZ, freq));
/* Warning: Some devices just use different bits for the same sources for no
* apparent reason. *Always* double-check the TRM before trusting this macro. */
#define clock_configure_source(device, src, freq) \
clrsetbits_le32(&clk_rst->clk_src_##device, \
CLK_SOURCE_MASK | CLK_DIVISOR_MASK, \
src << CLK_SOURCE_SHIFT | CLK_DIVIDER(TEGRA_##src##_KHZ, freq));
clock_configure_irregular_source(device, src, freq, src);
enum clock_source { /* Careful: Not true for all sources, always check TRM! */
PLLP = 0,
@ -220,8 +246,14 @@ enum clock_source { /* Careful: Not true for all sources, always check TRM! */
int clock_get_osc_khz(void);
void clock_early_uart(void);
void clock_external_output(int clk_id);
void clock_cpu0_config_and_reset(void * entry);
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w);
void clock_halt_avp(void);
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
void clock_init(void);
void clock_init_arm_generic_timer(void);
void sor_clock_stop(void);
void sor_clock_start(void);
#endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */

View File

@ -17,6 +17,166 @@
#ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__
#define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__
/* ardisplay.h */
#define DC_CMD_DISPLAY_WINDOW_HEADER_0 0x42
#define DC_COM_CRC_CONTROL_0 0x300
#define DC_COM_CRC_CHECKSUM_0 0x301
#define DC_COM_PIN_OUTPUT_ENABLE0_0 0x302
#define DC_COM_PIN_OUTPUT_ENABLE1_0 0x303
#define DC_COM_PIN_OUTPUT_ENABLE2_0 0x304
#define DC_COM_PIN_OUTPUT_ENABLE3_0 0x305
#define DC_CMD_STATE_ACCESS_0 0x40
#define DC_DISP_DISP_CLOCK_CONTROL_0 0x42e
#define DC_DISP_DISP_TIMING_OPTIONS_0 0x405
#define DC_DISP_REF_TO_SYNC_0 0x406
#define DC_DISP_SYNC_WIDTH_0 0x407
#define DC_DISP_BACK_PORCH_0 0x408
#define DC_DISP_DISP_ACTIVE_0 0x409
#define DC_DISP_FRONT_PORCH_0 0x40a
#define DC_DISP_DISP_WIN_OPTIONS_0 0x402
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT 25
#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_FIELD (0x1 << DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT)
#define DC_DISP_DISP_SIGNAL_OPTIONS0_0 0x400
#define DC_DISP_BLEND_BACKGROUND_COLOR_0 0x4e4
#define DC_CMD_DISPLAY_COMMAND_0 0x32
#define DC_CMD_STATE_CONTROL_0 0x41
#define DC_CMD_DISPLAY_POWER_CONTROL_0 0x36
/* ardisplay_a.h */
#define DC_WIN_A_WIN_OPTIONS_0 0x700
#define DC_WIN_A_BYTE_SWAP_0 0x701
#define DC_WIN_A_BUFFER_CONTROL_0 0x702
#define DC_WIN_A_COLOR_DEPTH_0 0x703
#define DC_WIN_A_POSITION_0 0x704
#define DC_WIN_A_SIZE_0 0x705
#define DC_WIN_A_PRESCALED_SIZE_0 0x706
#define DC_WIN_A_H_INITIAL_DDA_0 0x707
#define DC_WIN_A_V_INITIAL_DDA_0 0x708
#define DC_WIN_A_DDA_INCREMENT_0 0x709
#define DC_WIN_A_LINE_STRIDE_0 0x70a
#define DC_WIN_A_DV_CONTROL_0 0x70e
#define DC_WIN_A_BLEND_LAYER_CONTROL_0 0x716
#define DC_WIN_A_BLEND_MATCH_SELECT_0 0x717
#define DC_WIN_A_BLEND_NOMATCH_SELECT_0 0x718
#define DC_WIN_A_BLEND_ALPHA_1BIT_0 0x719
#define DC_WINBUF_A_START_ADDR_HI_0 0x80d
#define DC_WINBUF_A_ADDR_H_OFFSET_0 0x806
#define DC_WINBUF_A_ADDR_V_OFFSET_0 0x808
/* ardisplay_bd.h */
#define DC_B_WIN_BD_SIZE_0 0xd85
#define DC_B_WIN_BD_PRESCALED_SIZE_0 0xd86
#define DC_B_WIN_BD_LINE_STRIDE_0 0xd8a
#define DC_B_WIN_BD_COLOR_DEPTH_0 0xd83
#define DC_B_WINBUF_BD_START_ADDR_0 0xdc0
#define DC_B_WIN_BD_DDA_INCREMENT_0 0xd89
#define DC_B_WIN_BD_WIN_OPTIONS_0 0xd80
#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT 30
#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_FIELD (0x1 << DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT)
#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_ENABLE (1)
/* arsor.h */
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 0x13
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 0x5c
#define SOR_NV_PDISP_SOR_PLL0_0 0x17
#define SOR_NV_PDISP_SOR_PLL1_0 0x18
#define SOR_NV_PDISP_SOR_PLL2_0 0x19
#define SOR_NV_PDISP_SOR_PLL3_0 0x1a
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT 22
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT)
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT 0
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT 2
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT 24
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT 23
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT 25
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0 0x4e
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0 0x52
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0 0x56
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 0x5c
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT 8
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD (0xff << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT 22
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD (0x1 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0 0x1c
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 0x13
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0 0x4c
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0 0x21
#define SOR_NV_PDISP_SOR_DP_TPG_0 0x6d
#define SOR_NV_PDISP_HEAD_STATE1_0 0x7
#define SOR_NV_PDISP_HEAD_STATE2_0 0x9
#define SOR_NV_PDISP_HEAD_STATE3_0 0xb
#define SOR_NV_PDISP_HEAD_STATE4_0 0xd
#define SOR_NV_PDISP_SOR_STATE1_0 0x4
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT 12
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_FIELD (0x1 << SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT 13
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_FIELD (0x1 << SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT 8
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_LVDS_CUSTOM (0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_A (8)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_B (9)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_CUSTOM (15)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_ACTIVE_RASTER (0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_COMPLETE_RASTER (1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_NON_ACTIVE_RASTER (2)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT 6
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_FIELD (0x3 << SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT 4
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_FIELD (0x3 << SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_NONE (0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD0 (1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD1 (2)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_BOTH (3)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT 0
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_NONE (0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD0 (1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD1 (2)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0 0x58
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT 24
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_FIELD (0x1 << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT 16
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_FIELD (0xf << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT 8
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_FIELD (0x7f << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT 0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_FIELD (0x3f << SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT 2
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_FIELD (0x7f << SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT 17
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_DEFAULTVAL (0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_16_422 (1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_18_444 (2)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_20_422 (3)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_422 (4)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_444 (5)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_30_444 (6)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_32_422 (7)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_36_444 (8)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_48_444 (9)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0 0x11
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0 0x64
#define SOR_NV_PDISP_SOR_DP_SPARE0_0 0x60
#define SOR_NV_PDISP_SOR_PWR_0 0x15
#define SOR_NV_PDISP_SOR_STATE0_0 0x3
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0 0x2
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0 0x1
/* ardpaux.h */
#define DPAUX_DP_AUXDATA_READ_W0 0x19
void setup_display(struct soc_nvidia_tegra124_config *config);
void init_dca_regs(void);
void init_dpaux_regs(void);

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@ -27,20 +27,20 @@
* SUCH DAMAGE.
*/
.align 6
.align 2
.arm
.global cpug_stack_pointer
cpug_stack_pointer:
.global maincpu_stack_pointer
maincpu_stack_pointer:
.word 0
.global cpug_entry_point
cpug_entry_point:
.global maincpu_entry_point
maincpu_entry_point:
.word 0
.global cpug_setup
.type cpug_setup, function
cpug_setup:
.global maincpu_setup
.type maincpu_setup, function
maincpu_setup:
/*
* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
@ -50,7 +50,7 @@ cpug_entry_point:
*/
msr cpsr_cxf, #0xdf
ldr sp, cpug_stack_pointer
ldr sp, maincpu_stack_pointer
eor lr, lr
ldr r0, cpug_entry_point
ldr r0, maincpu_entry_point
bx r0

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@ -0,0 +1,29 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __SOC_NVIDIA_TEGRA124_MAINCPU_H__
#define __SOC_NVIDIA_TEGRA124_MAINCPU_H__
#include <stdint.h>
extern u32 maincpu_stack_pointer;
extern u32 maincpu_entry_point;
void maincpu_setup(void);
#endif /* __SOC_NVIDIA_TEGRA124_MAINCPU_H__ */

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@ -0,0 +1,47 @@
/*
* Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _TEGRA124_MC_H_
#define _TEGRA124_MC_H_
#include <stdint.h>
// Memory Controller registers we need/care about
struct tegra_mc_regs {
u32 reserved0[4];
u32 mc_smmu_config;
u32 mc_smmu_tlb_config;
u32 mc_smmu_ptc_config;
u32 mc_smmu_ptb_asid;
u32 mc_smmu_ptb_data;
u32 reserved1[3];
u32 mc_smmu_tlb_flush;
u32 mc_smmu_ptc_flush;
u32 reserved2[6];
u32 mc_emem_cfg;
u32 mc_emem_adr_cfg;
u32 mc_emem_adr_cfg_dev0;
u32 mc_emem_adr_cfg_dev1;
u32 reserved3[12];
u32 mc_emem_arb_reserved[28];
u32 reserved4[338];
u32 mc_vpr_bom;
u32 mc_vpr_size;
u32 mc_vpr_ctrl;
};
#endif /* _TEGRA124_MC_H_ */

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@ -184,7 +184,7 @@ enum {
PINMUX_CONSTANTS(208, DAP1_DOUT, N2, I2S0, DAP1, NOR, SATA),
PINMUX_CONSTANTS(209, DAP1_SCLK, N3, I2S0, DAP1, NOR, RES3),
PINMUX_CONSTANTS(210, DAP_MCLK1_REQ, EE2, DAP, DAP1, SATA, RES3),
PINMUX_CONSTANTS(211, DAP_MCLK1, W4, EXTPERHIP1, DAP2, RES2, RES3),
PINMUX_CONSTANTS(211, DAP_MCLK1, W4, EXTPERIPH1, DAP2, RES2, RES3),
PINMUX_CONSTANTS(212, SPDIF_IN, K6, SPDIF, RES1, RES2, I2C3),
PINMUX_CONSTANTS(213, SPDIF_OUT, K5, SPDIF, RES1, RES2, I2C3),
PINMUX_CONSTANTS(214, DAP2_FS, A2, I2S1, DAP2, NOR, RES3),

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@ -885,11 +885,8 @@ struct tegra_dc_dp_link_config {
* having two channels.
*/
struct tegra_dc_sor_data {
struct tegra_dc *dc;
void *base;
u8 portnum; /* 0 or 1 */
const struct tegra_dc_dp_link_config *link_cfg;
int power_is_up;
};

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@ -26,6 +26,7 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <timer.h>
#include <arch/cache.h>
#include <arch/io.h>
#include <console/console.h>
@ -49,6 +50,13 @@
#define SPI_MAX_TRANSFER_BYTES_FIFO (64 * SPI_PACKET_SIZE_BYTES)
#define SPI_MAX_TRANSFER_BYTES_DMA (65535 * SPI_PACKET_SIZE_BYTES)
/*
* This is used to workaround an issue seen where it may take some time for
* packets to show up in the FIFO after they have been received and the
* BLOCK_COUNT has been incremented.
*/
#define SPI_FIFO_XFER_TIMEOUT_US 1000
/* COMMAND1 */
#define SPI_CMD1_GO (1 << 31)
#define SPI_CMD1_M_S (1 << 30)
@ -89,19 +97,23 @@
#define SPI_STATUS_BLOCK_COUNT_SHIFT 0
/* SPI_FIFO_STATUS */
#define SPI_FIFO_STATUS_CS_INACTIVE (1 << 31)
#define SPI_FIFO_STATUS_FRAME_END (1 << 30)
#define SPI_FIFO_STATUS_RX_FIFO_FLUSH (1 << 15)
#define SPI_FIFO_STATUS_TX_FIFO_FLUSH (1 << 14)
#define SPI_FIFO_STATUS_ERR (1 << 8)
#define SPI_FIFO_STATUS_TX_FIFO_OVF (1 << 7)
#define SPI_FIFO_STATUS_TX_FIFO_UNR (1 << 6)
#define SPI_FIFO_STATUS_RX_FIFO_OVF (1 << 5)
#define SPI_FIFO_STATUS_RX_FIFO_UNR (1 << 4)
#define SPI_FIFO_STATUS_TX_FIFO_FULL (1 << 3)
#define SPI_FIFO_STATUS_TX_FIFO_EMPTY (1 << 2)
#define SPI_FIFO_STATUS_RX_FIFO_FULL (1 << 1)
#define SPI_FIFO_STATUS_RX_FIFO_EMPTY (1 << 0)
#define SPI_FIFO_STATUS_CS_INACTIVE (1 << 31)
#define SPI_FIFO_STATUS_FRAME_END (1 << 30)
#define SPI_FIFO_STATUS_RX_FIFO_FULL_COUNT_MASK 0x7f
#define SPI_FIFO_STATUS_RX_FIFO_FULL_COUNT_SHIFT 23
#define SPI_FIFO_STATUS_TX_FIFO_EMPTY_COUNT_MASK 0x7f
#define SPI_FIFO_STATUS_TX_FIFO_EMPTY_COUNT_SHIFT 16
#define SPI_FIFO_STATUS_RX_FIFO_FLUSH (1 << 15)
#define SPI_FIFO_STATUS_TX_FIFO_FLUSH (1 << 14)
#define SPI_FIFO_STATUS_ERR (1 << 8)
#define SPI_FIFO_STATUS_TX_FIFO_OVF (1 << 7)
#define SPI_FIFO_STATUS_TX_FIFO_UNR (1 << 6)
#define SPI_FIFO_STATUS_RX_FIFO_OVF (1 << 5)
#define SPI_FIFO_STATUS_RX_FIFO_UNR (1 << 4)
#define SPI_FIFO_STATUS_TX_FIFO_FULL (1 << 3)
#define SPI_FIFO_STATUS_TX_FIFO_EMPTY (1 << 2)
#define SPI_FIFO_STATUS_RX_FIFO_FULL (1 << 1)
#define SPI_FIFO_STATUS_RX_FIFO_EMPTY (1 << 0)
/* SPI_DMA_CTL */
#define SPI_DMA_CTL_DMA (1 << 31)
@ -129,26 +141,32 @@ static struct tegra_spi_channel tegra_spi_channels[] = {
{
.slave = { .bus = 1, },
.regs = (struct tegra_spi_regs *)TEGRA_SPI1_BASE,
.req_sel = APBDMA_SLAVE_SL2B1,
},
{
.slave = { .bus = 2, },
.regs = (struct tegra_spi_regs *)TEGRA_SPI2_BASE,
.req_sel = APBDMA_SLAVE_SL2B2,
},
{
.slave = { .bus = 3, },
.regs = (struct tegra_spi_regs *)TEGRA_SPI3_BASE,
.req_sel = APBDMA_SLAVE_SL2B3,
},
{
.slave = { .bus = 4, },
.regs = (struct tegra_spi_regs *)TEGRA_SPI4_BASE,
.req_sel = APBDMA_SLAVE_SL2B4,
},
{
.slave = { .bus = 5, },
.regs = (struct tegra_spi_regs *)TEGRA_SPI5_BASE,
.req_sel = APBDMA_SLAVE_SL2B5,
},
{
.slave = { .bus = 6, },
.regs = (struct tegra_spi_regs *)TEGRA_SPI6_BASE,
.req_sel = APBDMA_SLAVE_SL2B6,
},
};
@ -382,12 +400,32 @@ static void tegra_spi_pio_start(struct tegra_spi_channel *spi)
setbits_le32(&spi->regs->command1, SPI_CMD1_GO);
}
static inline u32 rx_fifo_count(struct tegra_spi_channel *spi)
{
return (read32(&spi->regs->fifo_status) >>
SPI_FIFO_STATUS_RX_FIFO_FULL_COUNT_SHIFT) &
SPI_FIFO_STATUS_RX_FIFO_FULL_COUNT_MASK;
}
static int tegra_spi_pio_finish(struct tegra_spi_channel *spi)
{
u8 *p = spi->in_buf;
struct mono_time start;
struct rela_time rt;
clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN);
/*
* Allow some time in case the Rx FIFO does not yet have
* all packets pushed into it. See chrome-os-partner:24215.
*/
timer_monotonic_get(&start);
do {
if (rx_fifo_count(spi) == spi_byte_count(spi))
break;
rt = current_time_from(&start);
} while (rela_time_in_microseconds(&rt) < SPI_FIFO_XFER_TIMEOUT_US);
while (!(read32(&spi->regs->fifo_status) &
SPI_FIFO_STATUS_RX_FIFO_EMPTY)) {
*p = read8(&spi->regs->rx_fifo);
@ -408,13 +446,20 @@ static void setup_dma_params(struct tegra_spi_channel *spi,
struct apb_dma_channel *dma)
{
/* APB bus width = 8-bits, address wrap for each word */
clrbits_le32(&dma->regs->apb_seq, 0x7 << 28);
clrbits_le32(&dma->regs->apb_seq,
AHB_BUS_WIDTH_MASK << AHB_BUS_WIDTH_SHIFT);
/* AHB 1 word burst, bus width = 32 bits (fixed in hardware),
* no address wrapping */
clrsetbits_le32(&dma->regs->ahb_seq,
(0x7 << 24) | (0x7 << 16), 0x4 << 24);
/* Set ONCE mode to transfer one "blocK" at a time (64KB). */
setbits_le32(&dma->regs->csr, 1 << 27);
(AHB_BURST_MASK << AHB_BURST_SHIFT),
4 << AHB_BURST_SHIFT);
/* Set ONCE mode to transfer one "block" at a time (64KB) and enable
* flow control. */
clrbits_le32(&dma->regs->csr,
APB_CSR_REQ_SEL_MASK << APB_CSR_REQ_SEL_SHIFT);
setbits_le32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW |
(spi->req_sel << APB_CSR_REQ_SEL_SHIFT));
}
static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
@ -447,7 +492,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
write32((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr);
write32((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
setbits_le32(&spi->dma_out->regs->csr, APBDMACHAN_CSR_DIR);
setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_out);
write32(wcount, &spi->dma_out->regs->wcount);
} else {
@ -460,7 +505,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
write32((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr);
write32((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
clrbits_le32(&spi->dma_in->regs->csr, APBDMACHAN_CSR_DIR);
clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_in);
write32(wcount, &spi->dma_in->regs->wcount);
}
@ -844,7 +889,6 @@ static void *tegra_spi_cbfs_map(struct cbfs_media *media, size_t offset,
void *map;
DEBUG_SPI("tegra_spi_cbfs_map\n");
map = cbfs_simple_buffer_map(&spi->buffer, media, offset, count);
printk(BIOS_INFO, "%s: map: 0x%p\n", __func__, map);
return map;
}

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@ -47,9 +47,12 @@ enum spi_xfer_mode {
};
struct tegra_spi_channel {
struct spi_slave slave;
struct tegra_spi_regs *regs;
/* static configuration */
struct spi_slave slave;
unsigned int req_sel;
/* stuff that is specific to the attached device */
int rx_frame_header_enable;
u8 frame_header;
@ -58,7 +61,6 @@ struct tegra_spi_channel {
u8 *in_buf, *out_buf;
struct apb_dma_channel *dma_out, *dma_in;
enum spi_xfer_mode xfer_mode;
};
struct cbfs_media;

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@ -57,6 +57,8 @@ static void tegra124_uart_init(struct tegra124_uart *uart_ptr)
// Disable interrupts.
write8(0, &uart_ptr->ier);
// Force DTR and RTS to high.
write8(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
// Set line configuration, access divisor latches.
write8(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
// Set the divisor.