soc/intel/alderlake: Skip PCIe source clock assignment if incorrect

When an enabled root port without pcie_rp clock being specified, the
empty structure provides invalid info, which indicates '0' is the
clock source and request. If a root port does not use clock source, it
should still need to provide pcie_rp clock structure with flags set to
PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it
is considered that pcie_rp clock structure is not provided for that
root port.

Add check and skip for enabled root port that does not have clock
structure. In addition, a root port can not use a free running clock or
clock set to LAN.

Note that ClockUsage is either free running clock, LAN clock, or the
root port number which consumes the clock.

BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

src/soc/intel/alderlake/romstage/fsp_params.c

@@ -58,6 +58,10 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ
 			continue;
 		if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
 			continue;
+		if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) {
+			printk(BIOS_WARNING, "Missing root port clock structure definition\n");
+			continue;
+		}
 		if (clk_req_mapping & (1 << cfg[i].clk_req))
 			printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n"
 				, cfg[i].clk_req);