soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports

There's no dedicated south bridge any more and now we have integrated
FCHs in the SoCs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50209
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/picasso/fch.c

@@ -115,7 +115,7 @@ static void sb_rfmux_config_override(void)
 	}
 }
 
-static void sb_init_acpi_ports(void)
+static void fch_init_acpi_ports(void)
 {
 	u32 reg;
 
@@ -220,7 +220,7 @@ static void gpp_clk_setup(void)
 void fch_init(void *chip_info)
 {
 	i2c_soc_init();
-	sb_init_acpi_ports();
+	fch_init_acpi_ports();
 
 	acpi_pm_gpe_add_events_print_events();
 	gpio_add_events();

src/soc/amd/stoneyridge/southbridge.c

@@ -356,7 +356,7 @@ void sb_enable(struct device *dev)
 	printk(BIOS_DEBUG, "%s\n", __func__);
 }
 
-static void sb_init_acpi_ports(void)
+static void fch_init_acpi_ports(void)
 {
 	u32 reg;
 
@@ -406,7 +406,7 @@ void fch_init(void *chip_info)
 {
 	struct chipset_power_state *state;
 
-	sb_init_acpi_ports();
+	fch_init_acpi_ports();
 
 	state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state));
 	if (state) {