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mb/system76/{tgl,skl}/dt: Use comma separated list for arrays 

In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.

While on it, remove superfluous comments related to modified lines.

Change-Id: I75aeb46ea3b4a7c0a41dce375735e7b42ed59587
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78664
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2023-10-26 15:42:16 +02:00 committed by Felix Singer
parent d163253ba0
commit ee1fd54aef
7 changed files with 112 additions and 92 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
src/mainboard/system76/kbl-u/devicetree.cb
View File

@ -110,26 +110,30 @@ chip soc/intel/skylake
device ref igpu on end device ref igpu on end
device ref sa_thermal on end device ref sa_thermal on end
device ref south_xhci on device ref south_xhci on
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right [0] = USB2_PORT_MID(OC_SKIP), /* Type-A port right */
register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE [1] = USB2_PORT_FLEX(OC_SKIP), /* 3G / LTE */
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right [2] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port right */
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera [3] = USB2_PORT_FLEX(OC_SKIP), /* Camera */
register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth [4] = USB2_PORT_FLEX(OC_SKIP), /* Bluetooth */
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left [6] = USB2_PORT_FLEX(OC_SKIP), /* Type-A port left */
register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right [7] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port right */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port right */
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right [1] = USB3_PORT_DEFAULT(OC_SKIP), /* 4G */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type C port right */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port left */
}"
end end
device ref thermal on end device ref thermal on end
device ref sata on device ref sata on
register "SataSalpSupport" = "0" register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[2]" = "1"
register "SataSpeedLimit" = "2" register "SataSpeedLimit" = "2"
register "SataPortsEnable" = "{
[0] = 1,
[2] = 1,
}"
end end
device ref pcie_rp1 on device ref pcie_rp1 on
# Root port #1 x4 (TBT) # Root port #1 x4 (TBT)

34
src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
View File

@ -29,23 +29,27 @@ chip soc/intel/tigerlake
register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[4]" = "4"
end end
device ref south_xhci on device ref south_xhci on
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right) [0] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right) */
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right) [1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left) [3] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left) [4] = USB2_PORT_MID(OC_SKIP), /* USB 2.0 (Left) */
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint [5] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right) register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right) [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 (Right) */
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right) [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left) [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
}"
end end
device ref sata on device ref sata on
register "SataPortsEnable[0]" = "1" # HDD (SATA0B) register "SataPortsEnable" = "{
register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A) [0] = 1, /* HDD (SATA0B) */
[1] = 1, /* SSD1 (SATA1A) */
}"
end end
device ref pcie_rp5 on device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 5 (GLAN) # PCIe root port #5 x1, Clock 5 (GLAN)

34
src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
View File

@ -29,23 +29,27 @@ chip soc/intel/tigerlake
register "PcieClkSrcClkReq[7]" = "7" register "PcieClkSrcClkReq[7]" = "7"
end end
device ref south_xhci on device ref south_xhci on
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 2 (Right) [0] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 2 (Right) */
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left) [1] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Back) [2] = USB2_PORT_TYPE_C(OC_SKIP), /* USB 3.2 Gen 2 Type C (Back) */
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left) [5] = USB2_PORT_MID(OC_SKIP), /* USB 2.0 (Left) */
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key [8] = USB2_PORT_MID(OC_SKIP), /* Per-Key */
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right) register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left) [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 (Right) */
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Back) [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Back) */
}"
end end
device ref sata on device ref sata on
register "SataPortsEnable[0]" = "1" # HDD (SATA0B) register "SataPortsEnable" = "{
register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A) [0] = 1, /* HDD (SATA0B) */
[1] = 1, /* SSD2 (SATA1A) */
}"
end end
device ref pcie_rp5 on device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 8 (GLAN) # PCIe root port #5 x1, Clock 8 (GLAN)

28
src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
View File

@ -41,19 +41,21 @@ chip soc/intel/tigerlake
end end
device ref tbt_dma0 on end # TYPEC1 device ref tbt_dma0 on end # TYPEC1
device ref south_xhci on device ref south_xhci on
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left) [0] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 1) [2] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right 1) */
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 2) [3] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right 2) */
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key [4] = USB2_PORT_MID(OC_SKIP), /* Per-Key */
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1 [8] = USB2_PORT_TYPE_C(OC_SKIP), /* TYPEC1 */
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left) register "usb3_ports" = "{
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 1) [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 2) [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Right 1) */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Right 2) */
}"
end end
device ref sata on device ref sata on
register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A) register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A)

26
src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
View File

@ -51,18 +51,20 @@ chip soc/intel/tigerlake
end end
device ref south_xhci on device ref south_xhci on
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # UJ_USB1 [0] = USB2_PORT_MID(OC_SKIP), /* UJ_USB1 */
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 [1] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC1 */
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1 [2] = USB2_PORT_MID(OC_SKIP), /* J_USB3_1 */
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint [4] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 [5] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC2 */
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera [6] = USB2_PORT_MID(OC_SKIP), /* Camera */
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH0 register "usb3_ports" = "{
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1 [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 CH0 */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1 [2] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_1 */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 CH1 */
}"
# ACPI # ACPI
chip drivers/usb/acpi chip drivers/usb/acpi

28
src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
View File

@ -51,19 +51,21 @@ chip soc/intel/tigerlake
end end
device ref south_xhci on device ref south_xhci on
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2 [0] = USB2_PORT_MID(OC_SKIP), /* J_USB3_2 */
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 [1] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC1 */
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1 [2] = USB2_PORT_MID(OC_SKIP), /* J_USB3_1 */
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint [4] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 [5] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC2 */
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera [6] = USB2_PORT_MID(OC_SKIP), /* Camera */
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2 register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH0 [0] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_2 */
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1 [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 CH0 */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1 [2] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_1 */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 CH1 */
}"
# ACPI # ACPI
chip drivers/usb/acpi chip drivers/usb/acpi
device ref xhci_root_hub on device ref xhci_root_hub on

20
src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
View File

@ -52,15 +52,17 @@ chip soc/intel/tigerlake
end end
device ref south_xhci on device ref south_xhci on
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1 [0] = USB2_PORT_MID(OC_SKIP), /* J_USB3_1 */
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2 [1] = USB2_PORT_MID(OC_SKIP), /* J_USB3_2 */
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 [2] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC1 */
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera [6] = USB2_PORT_MID(OC_SKIP), /* Camera */
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1 register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2 [0] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_1 */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_2 */
}"
# ACPI # ACPI
chip drivers/usb/acpi chip drivers/usb/acpi
device ref xhci_root_hub on device ref xhci_root_hub on