mb/google/zork: use gpio.h include

Replace the amdblocks/gpio.h, amdblocks/gpio_defs.h and soc/gpio.h
includes with the common gpio.h which will include soc/gpio.h which will
include amdblocks/gpio.h which will include amdblocks/gpio_defs.h in the
AMD SoC case.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I37a33dd8821a00b7edfd1e5b593f71bea0e77630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70434
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>

src/mainboard/google/zork/mainboard.c

@@ -6,14 +6,12 @@
 #include <acpi/acpi.h>
 #include <acpi/acpigen.h>
 #include <amdblocks/amd_pci_util.h>
-#include <amdblocks/gpio.h>
 #include <amdblocks/smi.h>
 #include <baseboard/variants.h>
 #include <boardid.h>
 #include <gpio.h>
 #include <smbios.h>
 #include <soc/cpu.h>
-#include <soc/gpio.h>
 #include <soc/pci_devs.h>
 #include <soc/platform_descriptors.h>
 #include <soc/southbridge.h>

src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c

@@ -3,7 +3,6 @@
 #include <baseboard/variants.h>
 #include <delay.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 #include <soc/smi.h>
 #include <variant/gpio.h>
 

src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c

@@ -5,7 +5,6 @@
 #include <delay.h>
 #include <ec/google/chromeec/ec.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 #include <soc/smi.h>
 #include <variant/gpio.h>
 

src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h

@@ -4,8 +4,7 @@
 #define __BASEBOARD_GPIO_H__
 
 #ifndef __ACPI__
-#include <amdblocks/gpio_defs.h>
-#include <soc/gpio.h>
+#include <gpio.h>
 
 #if CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE)
 #define EC_IN_RW_OD		GPIO_130

src/mainboard/google/zork/variants/baseboard/ramstage_common.c

@@ -9,7 +9,7 @@
 #include <drivers/i2c/hid/chip.h>
 #include <drivers/usb/acpi/chip.h>
 #include <ec/google/chromeec/ec.h>
-#include <soc/gpio.h>
+#include <gpio.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 

src/mainboard/google/zork/variants/baseboard/tpm_tis.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <gpio.h>
 #include <security/tpm/tis.h>
-#include <soc/gpio.h>
 #include <variant/gpio.h>
 
 int tis_plat_irq_status(void)

src/mainboard/google/zork/variants/berknip/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 #include <ec/google/chromeec/ec.h>
 
 static const struct soc_amd_gpio berknip_bid1_gpio_set_stage_ram[] = {

src/mainboard/google/zork/variants/dalboz/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 #include <ec/google/chromeec/ec.h>
 
 /* This table is used by dalboz variant with board version < 2. */

src/mainboard/google/zork/variants/dirinboz/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 #include <ec/google/chromeec/ec.h>
 
 static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {

src/mainboard/google/zork/variants/ezkinil/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 #include <ec/google/chromeec/ec.h>
 
 static const struct soc_amd_gpio ezkinil_bid1_gpio_set_stage_ram[] = {

src/mainboard/google/zork/variants/gumboz/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 
 static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = {
 	/* PEN_DETECT_ODL - no used */

src/mainboard/google/zork/variants/morphius/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 #include <ec/google/chromeec/ec.h>
 
 static const struct soc_amd_gpio morphius_bid1_gpio_set_stage_ram[] = {

src/mainboard/google/zork/variants/shuboz/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 #include <ec/google/chromeec/ec.h>
 
 static const struct soc_amd_gpio bid_gpio_set_stage_ram[] = {

src/mainboard/google/zork/variants/trembyle/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 #include <ec/google/chromeec/ec.h>
 
 static const struct soc_amd_gpio trembyle_bid1_bid2_gpio_set_stage_ram[] = {

src/mainboard/google/zork/variants/vilboz/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <soc/gpio.h>
 #include <ec/google/chromeec/ec.h>
 
 static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {

src/mainboard/google/zork/variants/woomax/gpio.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/variants.h>
-#include <soc/gpio.h>
+#include <gpio.h>
 
 static const struct soc_amd_gpio woomax_bid0_gpio_set_stage_ram[] = {
 	/* GPIO_4 NC */

src/mainboard/google/zork/verstage.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <amdblocks/gpio.h>
 #include <baseboard/variants.h>
+#include <gpio.h>
 #include <psp_verstage.h>
 #include <security/vboot/vboot_common.h>