GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 

Make sure the Skylake comment refers to the correct BWG paragraph and
update the text for all.

BUG=N/A
TEST=build

Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Wim Vervoorn 2020-02-03 15:25:49 +01:00 committed by Patrick Georgi
parent 84400180fa
commit ee38b991eb
4 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/cannonlake/bootblock/pch.c
View File

@ -168,8 +168,8 @@ void pch_early_iorange_init(void)
if (pch_check_decode_enable() == 0) { if (pch_check_decode_enable() == 0) {
io_enables = lpc_enable_fixed_io_ranges(io_enables); io_enables = lpc_enable_fixed_io_ranges(io_enables);
/* /*
* Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
* value program in LPC PCI offset 82h. * value programmed in LPC PCI offset 82h.
*/ */
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
/* /*

4
src/soc/intel/icelake/bootblock/pch.c
View File

@ -140,8 +140,8 @@ void pch_early_iorange_init(void)
if (pch_check_decode_enable() == 0) { if (pch_check_decode_enable() == 0) {
io_enables = lpc_enable_fixed_io_ranges(io_enables); io_enables = lpc_enable_fixed_io_ranges(io_enables);
/* /*
* Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
* value program in ESPI PCI offset 82h. * value programmed in ESPI PCI offset 82h.
*/ */
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
/* /*

6
src/soc/intel/skylake/bootblock/pch.c
View File

@ -135,9 +135,9 @@ void pch_early_iorange_init(void)
if (pch_check_decode_enable() == 0) { if (pch_check_decode_enable() == 0) {
io_enables = lpc_enable_fixed_io_ranges(io_enables); io_enables = lpc_enable_fixed_io_ranges(io_enables);
/* /*
* As per PCH BWG 2.5.16. * As per PCH BWG 2.5.1.6.
* Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
* value program in LPC PCI offset 82h. * value programmed in LPC PCI offset 82h.
*/ */
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
/* /*

4
src/soc/intel/tigerlake/bootblock/pch.c
View File

@ -165,8 +165,8 @@ void pch_early_iorange_init(void)
if (pch_check_decode_enable() == 0) { if (pch_check_decode_enable() == 0) {
io_enables = lpc_enable_fixed_io_ranges(io_enables); io_enables = lpc_enable_fixed_io_ranges(io_enables);
/* /*
* Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
* value program in ESPI PCI offset 82h. * value programmed in ESPI PCI offset 82h.
*/ */
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
/* /*