diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c
index 158601089e..72ea5b1455 100644
--- a/src/mainboard/google/veyron_brain/bootblock.c
+++ b/src/mainboard/google/veyron_brain/bootblock.c
@@ -70,7 +70,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c
index 158601089e..72ea5b1455 100644
--- a/src/mainboard/google/veyron_danger/bootblock.c
+++ b/src/mainboard/google/veyron_danger/bootblock.c
@@ -70,7 +70,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c
index 43af3f5fa1..b5b21b6c57 100644
--- a/src/mainboard/google/veyron_jerry/bootblock.c
+++ b/src/mainboard/google/veyron_jerry/bootblock.c
@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c
index 43af3f5fa1..b5b21b6c57 100644
--- a/src/mainboard/google/veyron_mighty/bootblock.c
+++ b/src/mainboard/google/veyron_mighty/bootblock.c
@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
index 43af3f5fa1..b5b21b6c57 100644
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ b/src/mainboard/google/veyron_pinky/bootblock.c
@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c
index f59f8e941d..b47e2e2db6 100644
--- a/src/mainboard/google/veyron_rialto/bootblock.c
+++ b/src/mainboard/google/veyron_rialto/bootblock.c
@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();
 }
diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c
index 43af3f5fa1..b5b21b6c57 100644
--- a/src/mainboard/google/veyron_speedy/bootblock.c
+++ b/src/mainboard/google/veyron_speedy/bootblock.c
@@ -68,7 +68,7 @@ void bootblock_mainboard_init(void)
 	/* spi2 for firmware ROM */
 	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
 	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
-	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	/* spi0 for chrome ec */
 	write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);