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nb/intel/sandybridge: Use write32p() 

Change-Id: I0984ff1d0b1908bfb7028910f2c6f1083e153520
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes Haouas 2022-12-04 09:16:07 +01:00 committed by Felix Held
parent a5e04af484
commit ee4646e70e
2 changed files with 9 additions and 9 deletions
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8
src/northbridge/intel/sandybridge/early_init.c
View File

@ -23,14 +23,14 @@ static void systemagent_vtd_init(void)
mchbar_write32(VTVC0BAR + 0, VTVC0_BASE | 1); mchbar_write32(VTVC0BAR + 0, VTVC0_BASE | 1);
/* Lock policies */ /* Lock policies */
write32((void *)(GFXVT_BASE + 0xff0), 0x80000000); write32p(GFXVT_BASE + 0xff0, 0x80000000);
const struct device *const azalia = pcidev_on_root(0x1b, 0); const struct device *const azalia = pcidev_on_root(0x1b, 0);
if (azalia && azalia->enabled) { if (azalia && azalia->enabled) {
write32((void *)(VTVC0_BASE + 0xff0), 0x20000000); write32p(VTVC0_BASE + 0xff0, 0x20000000);
write32((void *)(VTVC0_BASE + 0xff0), 0xa0000000); write32p(VTVC0_BASE + 0xff0, 0xa0000000);
} else { } else {
write32((void *)(VTVC0_BASE + 0xff0), 0x80000000); write32p(VTVC0_BASE + 0xff0, 0x80000000);
} }
} }

10
src/northbridge/intel/sandybridge/raminit_common.c
View File

@ -1513,7 +1513,7 @@ static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b)
for (j = 0; j < 16; j++) { for (j = 0; j < 16; j++) {
addr = 0x04000000 + channel_offset + 4 * j; addr = 0x04000000 + channel_offset + 4 * j;
write32((void *)addr, j & 2 ? b : a); write32p(addr, j & 2 ? b : a);
} }
sfence(); sfence();
@ -1538,11 +1538,11 @@ static void fill_pattern1(ramctr_timing *ctrl, int channel)
for (j = 0; j < 16; j++) { for (j = 0; j < 16; j++) {
addr = 0x04000000 + channel_offset + j * 4; addr = 0x04000000 + channel_offset + j * 4;
write32((void *)addr, 0xffffffff); write32p(addr, 0xffffffff);
} }
for (j = 0; j < 16; j++) { for (j = 0; j < 16; j++) {
addr = 0x04000000 + channel_offset + channel_step + j * 4; addr = 0x04000000 + channel_offset + channel_step + j * 4;
write32((void *)addr, 0); write32p(addr, 0);
} }
sfence(); sfence();
@ -1948,7 +1948,7 @@ static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno)
val = ~val; val = ~val;
addr = (1 << 26) + offset + i * step + j * 4; addr = (1 << 26) + offset + i * step + j * 4;
write32((void *)addr, val); write32p(addr, val);
} }
} }
} else { } else {
@ -1956,7 +1956,7 @@ static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno)
for (j = 0; j < 16; j++) { for (j = 0; j < 16; j++) {
const u32 val = pattern[i][j]; const u32 val = pattern[i][j];
addr = (1 << 26) + offset + i * step + j * 4; addr = (1 << 26) + offset + i * step + j * 4;
write32((void *)addr, val); write32p(addr, val);
} }
} }
sfence(); sfence();