From ee68b88babe604527e944224740fc2c6161cb351 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 2 Jul 2020 13:47:43 -0700 Subject: [PATCH] mb/google/kahlee: Drop macro H1_PCH_INT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change drops H1_PCH_INT macro for GPIO_9 since it is the same across all variants. Also, the name differed from the schematics version `H1_PCH_INT_ODL` creating confusion. Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/43015 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Kyösti Mälkki --- .../google/kahlee/variants/baseboard/include/baseboard/gpio.h | 3 --- src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h index 6c1c9418c2..88510722c2 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h @@ -11,9 +11,6 @@ # define MEM_CONFIG2 GPIO_131 # define MEM_CONFIG3 GPIO_132 -/* CR50 interrupt pin */ -#define H1_PCH_INT GPIO_9 - /* SPI Write protect */ #define CROS_WP_GPIO GPIO_122 #define GPIO_EC_IN_RW GPIO_15 diff --git a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c index 63625c408e..1c879529d4 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c +++ b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c @@ -6,5 +6,5 @@ int tis_plat_irq_status(void) { - return gpio_interrupt_status(H1_PCH_INT); + return gpio_interrupt_status(GPIO_9); }