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amdfam10 boards: Drop array bus_sb700 

Only bus_sb700[0] is evaluated.

Change-Id: Ie2cbbdebed3ae03da916d02919cd6a5d36f53562
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2019-01-03 11:39:03 +02:00
parent bf2d227135
commit ee7e1300f4
25 changed files with 32 additions and 157 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/mainboard/amd/mahogany_fam10/get_bus_conf.c
View File

@ -24,7 +24,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_sb700[2];
u32 apicid_sb700;
/*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void)
{
u32 apicid_base;
struct device *dev;
int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -61,17 +59,7 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
for (i = 0; i < 2; i++) {
bus_sb700[i] = 0;
}
bus_sb700[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

5
src/mainboard/amd/mahogany_fam10/irq_tables.c
View File

@ -40,7 +40,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu;
}
extern u8 bus_sb700[2];
unsigned long write_pirq_routing_table(unsigned long addr)
{
@ -65,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb700[0];
pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
@ -81,7 +80,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sb700[0], PCI_DEVFN(0x14, 4),
write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;

3
src/mainboard/amd/mahogany_fam10/mptable.c
View File

@ -20,7 +20,6 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
@ -45,7 +44,7 @@ static void *smp_write_config_table(void *v)
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
dev_find_slot(pirq_router_bus,
PCI_DEVFN(0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;

14
src/mainboard/amd/tilapia_fam10/get_bus_conf.c
View File

@ -24,7 +24,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_sb700[2];
u32 apicid_sb700;
/*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void)
{
u32 apicid_base;
struct device *dev;
int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -61,17 +59,7 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
for (i = 0; i < 2; i++) {
bus_sb700[i] = 0;
}
bus_sb700[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

5
src/mainboard/amd/tilapia_fam10/irq_tables.c
View File

@ -40,7 +40,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu;
}
extern u8 bus_sb700[2];
unsigned long write_pirq_routing_table(unsigned long addr)
{
@ -65,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb700[0];
pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
@ -81,7 +80,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sb700[0], PCI_DEVFN(0x14, 4),
write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;

3
src/mainboard/amd/tilapia_fam10/mptable.c
View File

@ -20,7 +20,6 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
@ -45,7 +44,7 @@ static void *smp_write_config_table(void *v)
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
dev_find_slot(pirq_router_bus,
PCI_DEVFN(0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;

14
src/mainboard/asus/m4a78-em/get_bus_conf.c
View File

@ -24,7 +24,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_sb700[2];
u32 apicid_sb700;
/*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void)
{
u32 apicid_base;
struct device *dev;
int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -61,17 +59,7 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
for (i = 0; i < 2; i++) {
bus_sb700[i] = 0;
}
bus_sb700[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

3
src/mainboard/asus/m4a78-em/mptable.c
View File

@ -20,7 +20,6 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
@ -45,7 +44,7 @@ static void *smp_write_config_table(void *v)
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
dev_find_slot(pirq_router_bus,
PCI_DEVFN(0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;

14
src/mainboard/asus/m4a785-m/get_bus_conf.c
View File

@ -24,7 +24,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_sb700[2];
u32 apicid_sb700;
/*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void)
{
u32 apicid_base;
struct device *dev;
int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -61,17 +59,7 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
for (i = 0; i < 2; i++) {
bus_sb700[i] = 0;
}
bus_sb700[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

3
src/mainboard/asus/m4a785-m/mptable.c
View File

@ -20,7 +20,6 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
@ -45,7 +44,7 @@ static void *smp_write_config_table(void *v)
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
dev_find_slot(pirq_router_bus,
PCI_DEVFN(0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;

14
src/mainboard/gigabyte/ma785gm/get_bus_conf.c
View File

@ -24,7 +24,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_sb700[2];
u32 apicid_sb700;
/*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void)
{
u32 apicid_base;
struct device *dev;
int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -61,17 +59,7 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
for (i = 0; i < 2; i++) {
bus_sb700[i] = 0;
}
bus_sb700[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

5
src/mainboard/gigabyte/ma785gm/irq_tables.c
View File

@ -40,7 +40,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu;
}
extern u8 bus_sb700[2];
unsigned long write_pirq_routing_table(unsigned long addr)
{
@ -65,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb700[0];
pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
@ -81,7 +80,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sb700[0], PCI_DEVFN(0x14, 4),
write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;

3
src/mainboard/gigabyte/ma785gm/mptable.c
View File

@ -20,7 +20,6 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
@ -45,7 +44,7 @@ static void *smp_write_config_table(void *v)
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
dev_find_slot(pirq_router_bus,
PCI_DEVFN(0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;

15
src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
View File

@ -24,7 +24,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_sb700[2];
u32 apicid_sb700;
/*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void)
{
u32 apicid_base;
struct device *dev;
int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -60,18 +58,7 @@ void get_bus_conf(void)
get_pci1234();
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
for (i = 0; i < 2; i++) {
bus_sb700[i] = 0;
}
bus_sb700[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

5
src/mainboard/gigabyte/ma785gmt/irq_tables.c
View File

@ -40,7 +40,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu;
}
extern u8 bus_sb700[2];
unsigned long write_pirq_routing_table(unsigned long addr)
{
@ -65,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb700[0];
pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
@ -81,7 +80,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sb700[0], PCI_DEVFN(0x14, 4),
write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;

3
src/mainboard/gigabyte/ma785gmt/mptable.c
View File

@ -20,7 +20,6 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
@ -45,7 +44,7 @@ static void *smp_write_config_table(void *v)
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
dev_find_slot(pirq_router_bus,
PCI_DEVFN(0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;

14
src/mainboard/gigabyte/ma78gm/get_bus_conf.c
View File

@ -24,7 +24,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_sb700[2];
u32 apicid_sb700;
/*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void)
{
u32 apicid_base;
struct device *dev;
int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -61,17 +59,7 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
for (i = 0; i < 2; i++) {
bus_sb700[i] = 0;
}
bus_sb700[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

5
src/mainboard/gigabyte/ma78gm/irq_tables.c
View File

@ -40,7 +40,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu;
}
extern u8 bus_sb700[2];
unsigned long write_pirq_routing_table(unsigned long addr)
{
@ -65,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb700[0];
pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
@ -81,7 +80,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sb700[0], PCI_DEVFN(0x14, 4),
write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;

3
src/mainboard/gigabyte/ma78gm/mptable.c
View File

@ -20,7 +20,6 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
@ -45,7 +44,7 @@ static void *smp_write_config_table(void *v)
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
dev_find_slot(pirq_router_bus,
PCI_DEVFN(0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;

14
src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
View File

@ -24,7 +24,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_sb700[2];
u32 apicid_sb700;
/*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void)
{
u32 apicid_base;
struct device *dev;
int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -61,17 +59,7 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
for (i = 0; i < 2; i++) {
bus_sb700[i] = 0;
}
bus_sb700[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

5
src/mainboard/iei/kino-780am2-fam10/irq_tables.c
View File

@ -40,7 +40,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu;
}
extern u8 bus_sb700[2];
unsigned long write_pirq_routing_table(unsigned long addr)
{
@ -65,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb700[0];
pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
@ -81,7 +80,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sb700[0], PCI_DEVFN(0x14, 4),
write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;

3
src/mainboard/iei/kino-780am2-fam10/mptable.c
View File

@ -20,7 +20,6 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
@ -45,7 +44,7 @@ static void *smp_write_config_table(void *v)
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
dev_find_slot(pirq_router_bus,
PCI_DEVFN(0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;

14
src/mainboard/jetway/pa78vm5/get_bus_conf.c
View File

@ -24,7 +24,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_sb700[2];
u32 apicid_sb700;
/*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void)
{
u32 apicid_base;
struct device *dev;
int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -61,17 +59,7 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
for (i = 0; i < 2; i++) {
bus_sb700[i] = 0;
}
bus_sb700[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

5
src/mainboard/jetway/pa78vm5/irq_tables.c
View File

@ -40,7 +40,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu;
}
extern u8 bus_sb700[2];
unsigned long write_pirq_routing_table(unsigned long addr)
{
@ -65,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb700[0];
pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
@ -81,7 +80,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sb700[0], PCI_DEVFN(0x14, 4),
write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;

3
src/mainboard/jetway/pa78vm5/mptable.c
View File

@ -21,7 +21,6 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
@ -46,7 +45,7 @@ static void *smp_write_config_table(void *v)
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
dev_find_slot(pirq_router_bus,
PCI_DEVFN(0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;