mb/msi/ms7721: Switch away from ROMCC_BOOTBLOCK
Renze Nicolai tested it on hardware: boots into Linux without problems. Change-Id: I17e09c366ae0c9c99d5c65dd1f00672697a7c709 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37737 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
Patrick Georgi
parent
b5ba8b6d1a
commit
ee8f969e1e
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@ -16,14 +16,10 @@
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# GNU General Public License for more details.
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#
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config BOARD_MSI_MS7721
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def_bool n
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if BOARD_MSI_MS7721
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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#select ROMCC_BOOTBLOCK
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select CPU_AMD_AGESA_FAMILY15_TN
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select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
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select SOUTHBRIDGE_AMD_AGESA_HUDSON
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@ -1,2 +1,2 @@
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#config BOARD_MSI_MS7721
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# bool"MS-7721 (FM2-A75MA-E35)"
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config BOARD_MSI_MS7721
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bool "MS-7721 (FM2-A75MA-E35)"
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@ -13,6 +13,8 @@
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# GNU General Public License for more details.
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#
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bootblock-y += bootblock.c
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romstage-y += buildOpts.c
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romstage-y += BiosCallOuts.c
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romstage-y += OemCustomize.c
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@ -0,0 +1,99 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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* Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
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* Copyright (C) 2016 Renze Nicolai <renze@rnplus.nl>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <device/pnp_ops.h>
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#include <device/pnp_type.h>
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#include <stdint.h>
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#include <southbridge/amd/common/amd_defs.h>
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#include <superio/fintek/common/fintek.h>
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#include <superio/fintek/f71869ad/f71869ad.h>
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#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
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/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
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#define SUPERIO_ADDRESS 0x4e
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#define SERIAL_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_SP1)
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#define GPIO_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_GPIO)
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/* GPIO configuration */
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static void gpio_init(pnp_devfn_t dev)
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{
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_write_config(dev, 0x60, 0x0a); //Base addr high
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pnp_write_config(dev, 0x61, 0x00); //Base addr low
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pnp_write_config(dev, 0xe0, 0x04); //GPIO1 output enable
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pnp_write_config(dev, 0xe1, 0xff); //GPIO1 output data
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pnp_write_config(dev, 0xe3, 0x04); //GPIO1 drive enable
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pnp_write_config(dev, 0xe4, 0x00); //GPIO1 PME enable
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pnp_write_config(dev, 0xe5, 0x00); //GPIO1 input detect select
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pnp_write_config(dev, 0xe6, 0x40); //GPIO1 event status
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pnp_write_config(dev, 0xd0, 0x00); //GPIO2 output enable
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pnp_write_config(dev, 0xd1, 0xff); //GPIO2 output data
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pnp_write_config(dev, 0xd3, 0x00); //GPIO2 drive enable
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pnp_write_config(dev, 0xc0, 0x00); //GPIO3 output enable
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pnp_write_config(dev, 0xc1, 0xff); //GPIO3 output data
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pnp_write_config(dev, 0xb0, 0x04); //GPIO4 output enable
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pnp_write_config(dev, 0xb1, 0x04); //GPIO4 output data
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pnp_write_config(dev, 0xb3, 0x04); //GPIO4 drive enable
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pnp_write_config(dev, 0xb4, 0x00); //GPIO4 PME enable
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pnp_write_config(dev, 0xb5, 0x00); //GPIO4 input detect select
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pnp_write_config(dev, 0xb6, 0x00); //GPIO4 event status
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pnp_write_config(dev, 0xa0, 0x00); //GPIO5 output enable
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pnp_write_config(dev, 0xa1, 0x1f); //GPIO5 output data
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pnp_write_config(dev, 0xa3, 0x00); //GPIO5 drive enable
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pnp_write_config(dev, 0xa4, 0x00); //GPIO5 PME enable
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pnp_write_config(dev, 0xa5, 0xff); //GPIO5 input detect select
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pnp_write_config(dev, 0xa6, 0xe0); //GPIO5 event status
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pnp_write_config(dev, 0x90, 0x00); //GPIO6 output enable
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pnp_write_config(dev, 0x91, 0xff); //GPIO6 output data
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pnp_write_config(dev, 0x93, 0x00); //GPIO6 drive enable
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pnp_write_config(dev, 0x80, 0x00); //GPIO7 output enable
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pnp_write_config(dev, 0x81, 0xff); //GPIO7 output data
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pnp_write_config(dev, 0x83, 0x00); //GPIO7 drive enable
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pnp_set_enable(dev, 1);
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pnp_exit_conf_state(dev);
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}
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static void sbxxx_enable_48mhzout(void)
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{
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/* most likely programming to 48MHz out signal */
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u32 reg32;
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reg32 = SB_MMIO_MISC32(0x28);
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reg32 &= 0xffc7ffff;
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reg32 |= 0x00100000;
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SB_MMIO_MISC32(0x28) = reg32;
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reg32 = SB_MMIO_MISC32(0x40);
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reg32 &= ~0x80u;
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SB_MMIO_MISC32(0x40) = reg32;
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}
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void bootblock_mainboard_early_init(void)
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{
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/* enable SIO clock */
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sbxxx_enable_48mhzout();
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/* Initialize GPIO registers */
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gpio_init(GPIO_DEV);
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/* Enable serial console */
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fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -15,116 +15,9 @@
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <device/pnp_ops.h>
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#include <device/pci_ops.h>
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#include <device/pnp.h>
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#include <stdint.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <southbridge/amd/common/amd_defs.h>
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#include <southbridge/amd/agesa/hudson/hudson.h>
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#include <superio/fintek/common/fintek.h>
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#include <superio/fintek/f71869ad/f71869ad.h>
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#define MMIO_NON_POSTED_START 0xfed00000
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#define MMIO_NON_POSTED_END 0xfedfffff
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#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
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/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
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#define SUPERIO_ADDRESS 0x4e
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#define SERIAL_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_SP1)
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#define GPIO_DEV PNP_DEV(SUPERIO_ADDRESS, F71869AD_GPIO)
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/* GPIO configuration */
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static void gpio_init(pnp_devfn_t dev)
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{
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_write_config(dev, 0x60, 0x0a); //Base addr high
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pnp_write_config(dev, 0x61, 0x00); //Base addr low
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pnp_write_config(dev, 0xe0, 0x04); //GPIO1 output enable
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pnp_write_config(dev, 0xe1, 0xff); //GPIO1 output data
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pnp_write_config(dev, 0xe3, 0x04); //GPIO1 drive enable
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pnp_write_config(dev, 0xe4, 0x00); //GPIO1 PME enable
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pnp_write_config(dev, 0xe5, 0x00); //GPIO1 input detect select
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pnp_write_config(dev, 0xe6, 0x40); //GPIO1 event status
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pnp_write_config(dev, 0xd0, 0x00); //GPIO2 output enable
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pnp_write_config(dev, 0xd1, 0xff); //GPIO2 output data
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pnp_write_config(dev, 0xd3, 0x00); //GPIO2 drive enable
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pnp_write_config(dev, 0xc0, 0x00); //GPIO3 output enable
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pnp_write_config(dev, 0xc1, 0xff); //GPIO3 output data
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pnp_write_config(dev, 0xb0, 0x04); //GPIO4 output enable
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pnp_write_config(dev, 0xb1, 0x04); //GPIO4 output data
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pnp_write_config(dev, 0xb3, 0x04); //GPIO4 drive enable
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pnp_write_config(dev, 0xb4, 0x00); //GPIO4 PME enable
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pnp_write_config(dev, 0xb5, 0x00); //GPIO4 input detect select
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pnp_write_config(dev, 0xb6, 0x00); //GPIO4 event status
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pnp_write_config(dev, 0xa0, 0x00); //GPIO5 output enable
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pnp_write_config(dev, 0xa1, 0x1f); //GPIO5 output data
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pnp_write_config(dev, 0xa3, 0x00); //GPIO5 drive enable
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pnp_write_config(dev, 0xa4, 0x00); //GPIO5 PME enable
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pnp_write_config(dev, 0xa5, 0xff); //GPIO5 input detect select
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pnp_write_config(dev, 0xa6, 0xe0); //GPIO5 event status
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pnp_write_config(dev, 0x90, 0x00); //GPIO6 output enable
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pnp_write_config(dev, 0x91, 0xff); //GPIO6 output data
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pnp_write_config(dev, 0x93, 0x00); //GPIO6 drive enable
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pnp_write_config(dev, 0x80, 0x00); //GPIO7 output enable
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pnp_write_config(dev, 0x81, 0xff); //GPIO7 output data
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pnp_write_config(dev, 0x83, 0x00); //GPIO7 drive enable
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pnp_set_enable(dev, 1);
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pnp_exit_conf_state(dev);
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}
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static void sbxxx_enable_48mhzout(void)
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{
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/* most likely programming to 48MHz out signal */
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u32 reg32;
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reg32 = SB_MMIO_MISC32(0x28);
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reg32 &= 0xffc7ffff;
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reg32 |= 0x00100000;
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SB_MMIO_MISC32(0x28) = reg32;
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reg32 = SB_MMIO_MISC32(0x40);
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reg32 &= ~0x80u;
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SB_MMIO_MISC32(0x40) = reg32;
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}
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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u8 byte;
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pci_devfn_t dev;
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/* enable SIO LPC decode */
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dev = PCI_DEV(0, 0x14, 3);
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byte = pci_read_config8(dev, 0x48);
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byte |= 3; /* 2e, 2f */
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pci_write_config8(dev, 0x48, byte);
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/* enable serial decode */
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byte = pci_read_config8(dev, 0x44);
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byte |= (1 << 6); /* 0x3f8 */
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pci_write_config8(dev, 0x44, byte);
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post_code(0x30);
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/* enable SB MMIO space */
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outb(0x24, 0xcd6);
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outb(0x1, 0xcd7);
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/* enable SIO clock */
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sbxxx_enable_48mhzout();
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/* Initialize GPIO registers */
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gpio_init(GPIO_DEV);
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/* Enable serial console */
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fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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