mb/google/geralt: Add NAU8318 support for Geralt

Add a config "USE_NAU8318" to enable NAU8318 support.

NAU8318 is another speaker used in Geralt. NAU8318 supports beep
function via GPIO control. So we configure the GPIO pins and pass them
to the payload.

BUG=b:250459803
BRANCH=none
TEST=Verify beep function through CLI in depthcharge successfully.

Change-Id: I21009a20809f398de4628ff0c11bcbd0e7591443
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73413
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Trevor Wu 2023-02-23 22:18:39 +08:00 committed by Martin L Roth
parent abe3c16df2
commit eeb5491b12
3 changed files with 12 additions and 3 deletions

View File

@ -68,6 +68,9 @@ choice
config USE_MAX98390
bool "MAX98390"
config USE_NAU8318
bool "NAU8318"
endchoice
endif

View File

@ -20,6 +20,7 @@ void setup_chromeos_gpios(void)
gpio_output(GPIO_EN_SPKR, 0);
gpio_output(GPIO_RST_SPKR_L, 0);
gpio_output(GPIO_XHCI_INIT_DONE, 0);
gpio_output(GPIO_BEEP_ON_OD, 0);
}
void fill_lb_gpios(struct lb_gpios *gpios)
@ -27,7 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
struct lb_gpio chromeos_gpios[] = {
{GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"},
{GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"},
{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"},
{GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
@ -46,6 +46,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{GPIO_RST_SPKR_L.id, ACTIVE_LOW, -1, "speaker reset"},
};
lb_add_gpios(gpios, max98390_gpios, ARRAY_SIZE(max98390_gpios));
} else if (CONFIG(USE_NAU8318)) {
struct lb_gpio nau8318_gpios[] = {
{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"},
{GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable"},
};
lb_add_gpios(gpios, nau8318_gpios, ARRAY_SIZE(nau8318_gpios));
}
}

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@ -8,9 +8,9 @@
#define GPIO_AP_DISP_BKLTEN GPIO(GPIO01)
#define GPIO_AP_EC_WARM_RST_REQ GPIO(DPI_HSYNC)
#define GPIO_AP_WP_ODL GPIO(GPIO15)
#define GPIO_BEEP_ON_OD GPIO(I2SIN_WS)
#define GPIO_BEEP_ON_OD GPIO(KPROW0)
#define GPIO_EC_AP_INT_ODL GPIO(DPI_DE)
#define GPIO_EN_SPKR GPIO(I2SIN_D2)
#define GPIO_EN_SPKR GPIO(I2SIN_D1)
#define GPIO_GSC_AP_INT_ODL GPIO(GPIO00)
#define GPIO_RST_SPKR_L GPIO(I2SO2_D1)
#define GPIO_XHCI_INIT_DONE GPIO(DPI_CK)