mb/google/geralt: Add NAU8318 support for Geralt
Add a config "USE_NAU8318" to enable NAU8318 support. NAU8318 is another speaker used in Geralt. NAU8318 supports beep function via GPIO control. So we configure the GPIO pins and pass them to the payload. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I21009a20809f398de4628ff0c11bcbd0e7591443 Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73413 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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@ -68,6 +68,9 @@ choice
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config USE_MAX98390
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bool "MAX98390"
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config USE_NAU8318
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bool "NAU8318"
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endchoice
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endif
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@ -20,6 +20,7 @@ void setup_chromeos_gpios(void)
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gpio_output(GPIO_EN_SPKR, 0);
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gpio_output(GPIO_RST_SPKR_L, 0);
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gpio_output(GPIO_XHCI_INIT_DONE, 0);
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gpio_output(GPIO_BEEP_ON_OD, 0);
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}
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void fill_lb_gpios(struct lb_gpios *gpios)
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@ -27,7 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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struct lb_gpio chromeos_gpios[] = {
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{GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"},
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{GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"},
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{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"},
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{GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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@ -46,6 +46,12 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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{GPIO_RST_SPKR_L.id, ACTIVE_LOW, -1, "speaker reset"},
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};
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lb_add_gpios(gpios, max98390_gpios, ARRAY_SIZE(max98390_gpios));
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} else if (CONFIG(USE_NAU8318)) {
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struct lb_gpio nau8318_gpios[] = {
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{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"},
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{GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable"},
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};
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lb_add_gpios(gpios, nau8318_gpios, ARRAY_SIZE(nau8318_gpios));
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}
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}
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@ -8,9 +8,9 @@
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#define GPIO_AP_DISP_BKLTEN GPIO(GPIO01)
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#define GPIO_AP_EC_WARM_RST_REQ GPIO(DPI_HSYNC)
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#define GPIO_AP_WP_ODL GPIO(GPIO15)
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#define GPIO_BEEP_ON_OD GPIO(I2SIN_WS)
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#define GPIO_BEEP_ON_OD GPIO(KPROW0)
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#define GPIO_EC_AP_INT_ODL GPIO(DPI_DE)
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#define GPIO_EN_SPKR GPIO(I2SIN_D2)
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#define GPIO_EN_SPKR GPIO(I2SIN_D1)
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#define GPIO_GSC_AP_INT_ODL GPIO(GPIO00)
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#define GPIO_RST_SPKR_L GPIO(I2SO2_D1)
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#define GPIO_XHCI_INIT_DONE GPIO(DPI_CK)
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