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nb/intel/haswell/hostbridge_regs.h: Clean up registers 

Add missing registers and sort them by ascending offsets.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: I98f836668144032d920b56afff878acc0a58ed82
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2020-07-22 01:02:46 +02:00
parent 28db21c462
commit eecd6843a2
1 changed files with 13 additions and 6 deletions
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19
src/northbridge/intel/haswell/hostbridge_regs.h
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@ -5,17 +5,15 @@
#define EPBAR 0x40
#define MCHBAR 0x48
#define PCIEXBAR 0x60
#define DMIBAR 0x68
#define GGC 0x50 /* GMCH Graphics Control */
#define GGC 0x50 /* GMCH Graphics Control */
#define GGC_DISABLE_VGA_IO_DECODE (1 << 1)
#define GGC_IGD_MEM_IN_32MB_UNITS(x) (((x) & 0x1f) << 3)
#define GGC_GTT_0MB (0 << 8)
#define GGC_GTT_1MB (1 << 8)
#define GGC_GTT_2MB (2 << 8)
#define DEVEN 0x54 /* Device Enable */
#define DEVEN 0x54 /* Device Enable */
#define DEVEN_D7EN (1 << 14)
#define DEVEN_D4EN (1 << 7)
#define DEVEN_D3EN (1 << 5)
@ -25,6 +23,15 @@
#define DEVEN_D1F2EN (1 << 1)
#define DEVEN_D0EN (1 << 0)
#define PAVPC 0x58
#define DPR 0x5c
#define PCIEXBAR 0x60
#define DMIBAR 0x68
#define MESEG_BASE 0x70 /* Management Engine Base */
#define MESEG_LIMIT 0x78 /* Management Engine Limit */
#define PAM0 0x80
#define PAM1 0x81
#define PAM2 0x82
@ -41,8 +48,6 @@
#define G_SMRAME (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
#define MESEG_BASE 0x70 /* Management Engine Base */
#define MESEG_LIMIT 0x78 /* Management Engine Limit */
#define REMAPBASE 0x90 /* Remap base */
#define REMAPLIMIT 0x98 /* Remap limit */
#define TOM 0xa0 /* Top of DRAM in memory controller space */
@ -57,4 +62,6 @@
#define CAPID0_A 0xe4
#define VTD_DISABLE (1 << 23)
#define CAPID0_B 0xe8
#endif /* __HASWELL_HOSTBRIDGE_REGS_H__ */