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AMD Socket ASB2 and AM3 support. 

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao 2010-04-23 17:35:37 +00:00 committed by Stefan Reinauer
parent eb75f652d3
commit eedf7a646c
15 changed files with 594 additions and 41 deletions
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2
src/cpu/amd/Kconfig
View File

@ -7,6 +7,8 @@ source src/cpu/amd/socket_939/Kconfig
source src/cpu/amd/socket_940/Kconfig source src/cpu/amd/socket_940/Kconfig
source src/cpu/amd/socket_AM2/Kconfig source src/cpu/amd/socket_AM2/Kconfig
source src/cpu/amd/socket_AM2r2/Kconfig source src/cpu/amd/socket_AM2r2/Kconfig
source src/cpu/amd/socket_AM3/Kconfig
source src/cpu/amd/socket_ASB2/Kconfig
source src/cpu/amd/socket_F/Kconfig source src/cpu/amd/socket_F/Kconfig
source src/cpu/amd/socket_F_1207/Kconfig source src/cpu/amd/socket_F_1207/Kconfig
source src/cpu/amd/socket_S1G1/Kconfig source src/cpu/amd/socket_S1G1/Kconfig

2
src/cpu/amd/Makefile.inc
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@ -5,6 +5,8 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_939) += socket_939
subdirs-$(CONFIG_CPU_AMD_SOCKET_940) += socket_940 subdirs-$(CONFIG_CPU_AMD_SOCKET_940) += socket_940
subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2
subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2
subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3
subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1 subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1
subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2 subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2
subdirs-$(CONFIG_CPU_AMD_LX) += model_lx subdirs-$(CONFIG_CPU_AMD_LX) += model_lx

82
src/cpu/amd/model_10xxx/defaults.h
View File

@ -290,7 +290,7 @@ static const struct {
/* errata 346 - Fam10 C2 /* errata 346 - Fam10 C2
* System software should set F3x188[22] to 1b. */ * System software should set F3x188[22] to 1b. */
{ 3, 0x188, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, { 3, 0x188, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL,
0x00400000, 0x00400000 }, 0x00400000, 0x00400000 },
/* L3 Control Register */ /* L3 Control Register */
@ -317,82 +317,82 @@ static const struct {
/* Errata 344 - Fam10 C2/D0 /* Errata 344 - Fam10 C2/D0
* System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */ * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
{ 0x60, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x60, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x61, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x61, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x62, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x62, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x63, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x63, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x64, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x64, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x65, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x65, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x66, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x66, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x67, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x67, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x68, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x68, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x70, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x70, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x71, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x71, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x72, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x72, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x73, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x73, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x74, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x74, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x75, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x75, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x76, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x76, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x77, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x77, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x78, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x78, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
/* Errata 354 - Fam10 C2 /* Errata 354 - Fam10 C2
* System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */ * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
{ 0x40, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x40, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x41, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x41, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x42, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x42, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x43, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x43, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x44, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x44, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x45, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x45, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x46, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x46, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x47, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x47, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x48, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x48, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x50, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x50, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x51, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x51, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x52, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x52, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x53, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x53, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x54, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x54, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x55, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x55, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x56, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x56, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x57, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x57, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
{ 0x58, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x58, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00000040, 0x00000040 }, 0x00000040, 0x00000040 },
/* Errata 327 - Fam10 C2/D0 /* Errata 327 - Fam10 C2/D0
@ -400,15 +400,15 @@ static const struct {
* (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
* Link Phy Impedance Register[RttIndex] * Link Phy Impedance Register[RttIndex]
* (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */ * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
{ 0xC0, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0xC0, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x40040000, 0xe01F0000 }, 0x40040000, 0xe01F0000 },
{ 0xD0, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0xD0, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x40040000, 0xe01F0000 }, 0x40040000, 0xe01F0000 },
{ 0x520A, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x520A, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
{ 0x530A, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x530A, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
{ 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,

164
src/cpu/amd/model_10xxx/mc_patch_01000086.h Normal file
View File

@ -0,0 +1,164 @@
/*
============================================================
(c) Advanced Micro Devices, Inc., 2004-2008
The enclosed microcode is intended to be used with AMD
Microprocessors. You may copy, view and install the
enclosed microcode only for development and deployment of
firmware, BIOS, or operating system code for computer
systems that contain AMD processors. You are not
authorized to use the enclosed microcode for any other
purpose.
THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR
IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT,
TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES
ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
AMD does not assume any responsibility for any errors which
may appear in this microcode or any other related
information provided to you by AMD, or result from use of
this microcode. AMD is not obligated to furnish, support,
or make any further information, software, technical
information, know-how, or show-how available related to this
microcode.
The microcode is provided with "RESTRICTED RIGHTS." Use,
duplication, or disclosure by the U.S. Government is subject
to the restrictions as set forth in FAR 52.227-14 and
DFAR252.227-7013, et seq., or its successor. Use of the
microcode by the U.S. Government constitutes
acknowledgement of AMD's proprietary rights in them.
============================================================
*/
0x08, 0x20, 0x01, 0x05, 0x86, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00,
0x04, 0xde, 0x30, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x41, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xa0, 0x09, 0x00, 0x00,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0x00, 0xfe, 0xbf, 0x07, 0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00,
0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03, 0x1f, 0xc0, 0x7f, 0xe0,
0xe0, 0xdf, 0xf0, 0x0f, 0x03, 0x00, 0xff, 0xdf, 0xff, 0x00, 0xfe, 0x03,
0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f, 0x01, 0xfc, 0x1b, 0xfe,
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0xff, 0x00, 0xfe, 0x0d, 0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37,
0xff, 0xf7, 0x00, 0xc0, 0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf,
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0x0f, 0xe0, 0x3f, 0xf0, 0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0,
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0x1e, 0x00, 0xf8, 0xff, 0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc,
0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, 0x81, 0x7f, 0x00, 0xff,
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164
src/cpu/amd/model_10xxx/mc_patch_010000b6.h Normal file
View File

@ -0,0 +1,164 @@
/*
============================================================
(c) Advanced Micro Devices, Inc., 2004-2008
The enclosed microcode is intended to be used with AMD
Microprocessors. You may copy, view and install the
enclosed microcode only for development and deployment of
firmware, BIOS, or operating system code for computer
systems that contain AMD processors. You are not
authorized to use the enclosed microcode for any other
purpose.
THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR
IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT,
TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES
ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
AMD does not assume any responsibility for any errors which
may appear in this microcode or any other related
information provided to you by AMD, or result from use of
this microcode. AMD is not obligated to furnish, support,
or make any further information, software, technical
information, know-how, or show-how available related to this
microcode.
The microcode is provided with "RESTRICTED RIGHTS." Use,
duplication, or disclosure by the U.S. Government is subject
to the restrictions as set forth in FAR 52.227-14 and
DFAR252.227-7013, et seq., or its successor. Use of the
microcode by the U.S. Government constitutes
acknowledgement of AMD's proprietary rights in them.
============================================================
*/
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0x01, 0xfc, 0x07, 0xfe, 0xf4, 0x0f, 0xdf, 0x5a, 0x4f, 0xa0, 0x3e, 0xe0,
0xd8, 0x3a, 0xfc, 0x32, 0x00, 0xc0, 0x01, 0x48, 0x3f, 0x80, 0xff, 0xc0,
0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, 0x00, 0xff, 0x86, 0x7f,
0xfc, 0x03, 0xf8, 0x0f, 0x01, 0xfc, 0x1b, 0xfe, 0x7b, 0x00, 0xe0, 0xff,
0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, 0x81, 0x7f, 0x00, 0xff,
0x3f, 0x80, 0x7f, 0xc3, 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
0xff, 0x3d, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
0xff, 0xc0, 0x3f, 0x80, 0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00,
0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x1e, 0x00, 0xf0, 0x1f, 0xf8, 0x07,
0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, 0x00, 0xfc, 0x7f, 0x0f,
0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, 0xc0, 0xbf, 0xe1, 0x1f,
0x07, 0x00, 0xfe, 0xbf, 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, 0xe0, 0x1f, 0xc0, 0x7f,
0x0f, 0xe0, 0xdf, 0xf0, 0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe,
0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

2
src/cpu/amd/model_10xxx/model_10xxx_init.c
View File

@ -135,8 +135,10 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x100f23 }, { X86_VENDOR_AMD, 0x100f23 },
{ X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */ { X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */
{ X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */ { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */
{ X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */
{ X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */ { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */
{ X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */
{ X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
{ X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
{ 0, 0 }, { 0, 0 },
}; };

4
src/cpu/amd/model_10xxx/update_microcode.c
View File

@ -47,7 +47,9 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
* 00100F22h (DR-B2) 1022h 01000095h * 00100F22h (DR-B2) 1022h 01000095h
* 00100F23h (DR-B3) 1022h 01000095h * 00100F23h (DR-B3) 1022h 01000095h
* 00100F42h (RB-C2) 1041h 01000086h * 00100F42h (RB-C2) 1041h 01000086h
* 00100F43h (RB-C3) 1043h 010000b6h
* 00100F62h (DA-C2) 1062h 0100009Fh * 00100F62h (DA-C2) 1062h 0100009Fh
* 00100F63h (DA-C3) 1043h 010000b6h
*/ */
#include CONFIG_AMD_UCODE_PATCH_FILE #include CONFIG_AMD_UCODE_PATCH_FILE
@ -71,7 +73,9 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) {
0x100f22, 0x1022, 0x100f22, 0x1022,
0x100f23, 0x1022, 0x100f23, 0x1022,
0x100f42, 0x1041, 0x100f42, 0x1041,
0x100f43, 0x1043,
0x100f62, 0x1062, 0x100f62, 0x1062,
0x100f63, 0x1043,
}; };
u32 new_id; u32 new_id;

47
src/cpu/amd/socket_AM3/Kconfig Normal file
View File

@ -0,0 +1,47 @@
config CPU_AMD_SOCKET_AM3
bool
select CPU_AMD_MODEL_10XXX
select HT3_SUPPORT
select PCI_IO_CFG_EXT
config CPU_SOCKET_TYPE
hex
default 0x11
depends on CPU_AMD_SOCKET_AM3
# DDR3 and REG
config DIMM_SUPPORT
hex
default 0x0005
depends on CPU_AMD_SOCKET_AM3
config EXT_RT_TBL_SUPPORT
bool
default n
depends on CPU_AMD_SOCKET_AM3
config EXT_CONF_SUPPORT
bool
default n
depends on CPU_AMD_SOCKET_AM3
config CBB
hex
default 0x0
depends on CPU_AMD_SOCKET_AM3
config CDB
hex
default 0x18
depends on CPU_AMD_SOCKET_AM3
config XIP_ROM_BASE
hex
default 0xfff80000
depends on CPU_AMD_SOCKET_AM3
config XIP_ROM_SIZE
hex
default 0x80000
depends on CPU_AMD_SOCKET_AM3

13
src/cpu/amd/socket_AM3/Makefile.inc Normal file
View File

@ -0,0 +1,13 @@
obj-y += socket_AM3.o
subdirs-y += ../model_10xxx
subdirs-y += ../quadcore
subdirs-y += ../mtrr
subdirs-y += ../microcode
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/pae
subdirs-y += ../../x86/smm
subdirs-y += ../../x86/mtrr
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc

23
src/cpu/amd/socket_AM3/chip.h Normal file
View File

@ -0,0 +1,23 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern struct chip_operations cpu_amd_socket_AM3_ops;
struct cpu_amd_socket_AM3_config {
};

25
src/cpu/amd/socket_AM3/socket_AM3.c Normal file
View File

@ -0,0 +1,25 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
#include "chip.h"
struct chip_operations cpu_amd_socket_AM3_ops = {
CHIP_NAME("socket AM3")
};

46
src/cpu/amd/socket_ASB2/Kconfig Normal file
View File

@ -0,0 +1,46 @@
config CPU_AMD_SOCKET_ASB2
bool
select CPU_AMD_MODEL_10XXX
select HT3_SUPPORT
select PCI_IO_CFG_EXT
config CPU_SOCKET_TYPE
hex
default 0x13
depends on CPU_AMD_SOCKET_ASB2
# DDR3 and REG
config DIMM_SUPPORT
hex
default 0x0005
depends on CPU_AMD_SOCKET_ASB2
config EXT_RT_TBL_SUPPORT
bool
default n
depends on CPU_AMD_SOCKET_ASB2
config EXT_CONF_SUPPORT
bool
default n
depends on CPU_AMD_SOCKET_ASB2
config CBB
hex
default 0x0
depends on CPU_AMD_SOCKET_ASB2
config CDB
hex
default 0x18
depends on CPU_AMD_SOCKET_ASB2
config XIP_ROM_BASE
hex
default 0xfff80000
depends on CPU_AMD_SOCKET_ASB2
config XIP_ROM_SIZE
hex
default 0x80000
depends on CPU_AMD_SOCKET_ASB2

13
src/cpu/amd/socket_ASB2/Makefile.inc Normal file
View File

@ -0,0 +1,13 @@
obj-y += socket_ASB2.o
subdirs-y += ../model_10xxx
subdirs-y += ../quadcore
subdirs-y += ../mtrr
subdirs-y += ../microcode
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/pae
subdirs-y += ../../x86/smm
subdirs-y += ../../x86/mtrr
cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc

23
src/cpu/amd/socket_ASB2/chip.h Normal file
View File

@ -0,0 +1,23 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern struct chip_operations cpu_amd_socket_ASB2_ops;
struct cpu_amd_socket_ASB2_config {
};

25
src/cpu/amd/socket_ASB2/socket_ASB2.c Normal file
View File

@ -0,0 +1,25 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
#include "chip.h"
struct chip_operations cpu_amd_socket_ASB2_ops = {
CHIP_NAME("socket ASB2")
};