diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index f32b3dcf47..7788a2da4e 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -118,7 +118,7 @@ addrsize_set_high:
 	/* Enable cache for our code in Flash because we do XIP here */
 	movl	$MTRR_PHYS_BASE(1), %ecx
 	xorl	%edx, %edx
-	movl	$CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax
+	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
 	wrmsr
 
 	movl	$MTRR_PHYS_MASK(1), %ecx
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index f84e85565e..9d50582232 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -304,7 +304,7 @@ no_msr_11e:
 	/* Cache the whole rom to fetch microcode updates */
 	movl	$MTRR_PHYS_BASE(1), %ecx
 	xorl	%edx, %edx
-	movl	$CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax
+	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
 	wrmsr
 
 	movl	$MTRR_PHYS_MASK(1), %ecx