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mb/google/dedede: Update the flash ROM layout for RW regions 

RW_LEGACY region needs to be 1 MiB to accommodate any alternate
firmware. Hence update the flash ROM layout as below:
* Grab ~512 KiB from each FW_MAIN_A/B regions and allocate them to
  RW_LEGACY region so that it grows to 1 MiB.
* Remove VBLOCK_DEV region which is not used.
* Re-size the ELOG region to 4 KiB since that is the maximum size of the
  ELOG mirror buffer.
* Resize RW_NVRAM, VBLOCK_A/B regions to 8 KiB since no more than that
  size is used in those regions.
* Resize SHARED_DATA region to 4 KiB since no more than that size is
  used in that region.
* Based on the resizing, allocate each FW_MAIN_A/B regions with 72 KiB.

BUG=b:167943992, b:167498108
TEST=Build and boot to OS in Drawlat. Ensure that the firmware test
setup and flash map test are successful. Ensure that the event logs are
synced properly between reboots. Ensure that the suspend/resume sequence
is working fine. Ensure that the ChromeOS firmware update completes
successfully for the boot image with updated flash map and the system
boots fine after the update.

Change-Id: I53ada5ac3bd73bea50f4dd4dd352556f1eda7838
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46569
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2020-10-19 22:08:25 -06:00 committed by Karthik Ramasubramanian
parent 488bbe2c88
commit eef5cadca8
1 changed files with 15 additions and 16 deletions
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31
src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd
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@ -4,29 +4,28 @@ FLASH@0xff000000 0x1000000 {
SI_ME@0x1000 0x380000 SI_ME@0x1000 0x380000
} }
SI_BIOS@0x381000 0xc7f000 { SI_BIOS@0x381000 0xc7f000 {
RW_LEGACY(CBFS)@0x0 0x1000 RW_LEGACY(CBFS)@0x0 0x100000
RW_SECTION_A@0x1000 0x420000 { RW_SECTION_A@0x100000 0x3a4800 {
VBLOCK_A@0x0 0x10000 VBLOCK_A@0x0 0x2000
FW_MAIN_A(CBFS)@0x10000 0x40ffc0 FW_MAIN_A(CBFS)@0x2000 0x3a27c0
RW_FWID_A@0x41ffc0 0x40 RW_FWID_A@0x3a47c0 0x40
} }
RW_SECTION_B@0x421000 0x420000 { RW_SECTION_B@0x4a4800 0x3a4800 {
VBLOCK_B@0x0 0x10000 VBLOCK_B@0x0 0x2000
FW_MAIN_B(CBFS)@0x10000 0x40ffc0 FW_MAIN_B(CBFS)@0x2000 0x3a27c0
RW_FWID_B@0x41ffc0 0x40 RW_FWID_B@0x3a47c0 0x40
} }
RW_MISC@0x841000 0x3e000 { RW_MISC@0x849000 0x36000 {
UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
RECOVERY_MRC_CACHE@0x0 0x10000 RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x20000 RW_MRC_CACHE@0x10000 0x20000
} }
RW_ELOG(PRESERVE)@0x30000 0x3000 RW_ELOG(PRESERVE)@0x30000 0x1000
RW_SHARED@0x33000 0x4000 { RW_SHARED@0x31000 0x1000 {
SHARED_DATA@0x0 0x2000 SHARED_DATA@0x0 0x1000
VBLOCK_DEV@0x2000 0x2000
} }
RW_VPD(PRESERVE)@0x37000 0x2000 RW_VPD(PRESERVE)@0x32000 0x2000
RW_NVRAM(PRESERVE)@0x39000 0x5000 RW_NVRAM(PRESERVE)@0x34000 0x2000
} }
# Make WP_RO region align with SPI vendor # Make WP_RO region align with SPI vendor
# memory protected range specification. # memory protected range specification.