S2885 winbond Superio all resource set

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/tyan/s2885/Config.lb

@@ -177,13 +177,20 @@ chip northbridge/amd/amdk8
                                 			irq 0x70 = 1
 							irq 0x72 = 12
 						end
-                        			device pnp 2e.6 off end #  CIR
+                        			device pnp 2e.6 off #  CIR
-                        			device pnp 2e.7 off end #  GAME_MIDI_GIPO1
+							io 0x60 = 0x100
+						end
+                        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
+							io 0x60 = 0x201
+							io 0x62 = 0x330
+							irq 0x70 = 9
+						end						
                         			device pnp 2e.8 off end #  GPIO2
                         			device pnp 2e.9 off end #  GPIO3
                         			device pnp 2e.a off end #  ACPI
                         			device pnp 2e.b on #  HW Monitor
  				 			io 0x60 = 0x290
+							irq 0x70 = 5
                 				end
 					end
 				end
@@ -192,6 +199,8 @@ chip northbridge/amd/amdk8
 				device pci 1.3 on end
 				device pci 1.5 on end
 				device pci 1.6 off end
+#                                register "ide0_enable" = "1"
+#                                register "ide1_enable" = "1"
 			end
 		end #  device pci 18.0 
 		

src/mainboard/tyan/s2885/Options.lb

@@ -32,6 +32,8 @@ uses LB_CKS_LOC
 uses MAINBOARD_PART_NUMBER
 uses MAINBOARD_VENDOR
 uses MAINBOARD
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
 uses CC
@@ -117,6 +119,8 @@ default CONFIG_IOAPIC=1
 ##
 default MAINBOARD_PART_NUMBER="Tyan"
 default MAINBOARD_VENDOR="s2885"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885
 
 ###
 ### LinuxBIOS layout values

src/mainboard/tyan/s2885/auto.c

@@ -50,22 +50,28 @@ static void soft2_reset(void)
 
 static void memreset_setup(void)
 {
+#if 0
    if (is_cpu_pre_c0()) {
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
    }
    else {
+#endif
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
+#if 0
    }
+#endif
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
+#if 0
    if (is_cpu_pre_c0()) {
         udelay(800);
         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
         udelay(90);
    }
+#endif
 }
 
 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
@@ -111,7 +117,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
 	};
 
 	if(maxnodes>2) {
-		print_debug("this mainboard is only designed for 2 cpus\r\n");
+//		print_debug("this mainboard is only designed for 2 cpus\r\n");
 		maxnodes=2;
 	}
 

src/mainboard/tyan/s2885/chip.h

@@ -2,5 +2,5 @@ extern struct chip_operations mainboard_tyan_s2885_ops;
 
 struct mainboard_tyan_s2885_config {
 	int fixup_scsi;
-	int fixup_vga;
+//	int fixup_vga;
 };

src/mainboard/tyan/s2885/irq_tables.c

@@ -18,7 +18,7 @@ const struct irq_routing_table intel_irq_routing_table = {
 	0x746b,         /* Device */
 	0,         /* Crap (miniport) */
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x35,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	0xd8,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
 		{3,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
 		{0x6,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},

src/southbridge/amd/amd8111/amd8111_usb.c

@@ -6,21 +6,16 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <device/chip.h>
-#include <device/smbus.h>
 #include <arch/io.h>
 #include "amd8111.h"
 
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-	pci_write_config32(dev, 0x44, 
+	pci_write_config32(dev, 0x70, 
 		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
-static struct smbus_bus_operations lops_smbus_bus = {
-	/* I haven't seen the 2.0 SMBUS controller used yet. */
-};
 static struct pci_operations lops_pci = {
 	.set_subsystem = lpci_set_subsystem,
 };
@@ -30,13 +25,12 @@ static struct device_operations smbus_ops = {
 	.enable_resources = pci_dev_enable_resources,
 	.init             = 0,
 	.scan_bus         = scan_static_bus,
-	.enable           = amd8111_enable,
+//	.enable           = amd8111_enable,
 	.ops_pci          = &lops_pci,
-	.ops_smbus_bus    = &lops_smbus_bus,
 };
 
 static struct pci_driver smbus_driver __pci_driver = {
 	.ops = &smbus_ops,
 	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_8111_SMB,
+	.device = PCI_DEVICE_ID_AMD_8111_USB,
 };

src/southbridge/amd/amd8151/amd8151_agp3.c

@@ -54,6 +54,10 @@ static void agp3dev_enable(device_t dev)
 #endif
 }
 
+static struct pci_operations pci_ops_pci_dev = {
+        .set_subsystem    = pci_dev_set_subsystem,
+};
+
 static struct device_operations agp3dev_ops = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
@@ -61,6 +65,7 @@ static struct device_operations agp3dev_ops = {
 	.init     = 0,
 	.scan_bus = 0,
 	.enable   = agp3dev_enable,
+	.ops_pci  = &pci_ops_pci_dev,
 };
 
 static struct pci_driver agp3dev_driver __pci_driver = {

src/superio/winbond/w83627hf/superio.c

@@ -201,11 +201,11 @@ static struct pnp_info pnp_dev_info[] = {
         // No 4 { 0,},
         { &ops, W83627HF_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
         { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-        { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
+        { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
         { &ops, W83627HF_GPIO2, },
         { &ops, W83627HF_GPIO3, },
-        { &ops, W83627HF_ACPI, PNP_IRQ0,  },
+        { &ops, W83627HF_ACPI, },
-        { &ops, W83627HF_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
+        { &ops, W83627HF_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
 };
 
 static void enable_dev(struct device *dev)