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mb/intel/tglrvp: Enable CpuReplacementCheck 

Enable CpuReplacementCheck for TGLRVP with a CPU socket.

Test=build and verified with tglrvp

Change-Id: I75b4a4609c172c341087077228e23c6d31a9e7e1
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
Jamie Ryu 2020-06-24 15:55:10 -07:00 committed by Patrick Georgi
parent 6aedba2f13
commit ef079c86ea
2 changed files with 6 additions and 0 deletions
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3
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
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@ -32,6 +32,9 @@ chip soc/intel/tigerlake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector
# CPU replacement check
register "CpuReplacementCheck" = "1"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"

3
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -32,6 +32,9 @@ chip soc/intel/tigerlake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector
# CPU replacement check
register "CpuReplacementCheck" = "1"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"