-Clean up some comments.
-Remove some white spaces. -Remove some leading zeros. -Fix a typo in LX code. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
Myles Watson
parent
fc01e5e3bb
commit
ef15ff4de4
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@ -91,12 +91,12 @@
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#define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D)
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#define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E)
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#define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F)
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#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x010)
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#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x011)
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#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x012)
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#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x013)
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#define MDD_PIN_OPT (MSR_SB_MDD + 0x015)
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#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x018)
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#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x10)
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#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x11)
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#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x12)
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#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x13)
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#define MDD_PIN_OPT (MSR_SB_MDD + 0x15)
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#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x18)
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/* GPIO */
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#define GPIOL_2_SET (1 << 2)
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@ -22,7 +22,7 @@
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#define Cx5536_ID ( 0x208F1022)
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/* SouthBridge Equates */
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/* SouthBridge Equates */
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#define CS5536_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */
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#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */
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#define MSR_SB ((CS5536_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */
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@ -33,11 +33,11 @@
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#define GPIO_IO_BASE 0x6100
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#define MFGPT_IO_BASE 0x6200
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#define ACPI_IO_BASE 0x9C00
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#define PMS_IO_BASE 0x9D00
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#define PMS_IO_BASE 0x9D00
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#define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15
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#define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */
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#define CHIPSET_DEV_NUM 15
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#define IDSEL_BASE 11 // bit 11 = device 1
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#define IDSEL_BASE 11 /* bit 11 = device 1 */
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/* Cs5536 as follows. */
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/* SB_GLIU */
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@ -50,8 +50,8 @@
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/* port6 - USB Controller #1 */
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/* port7 - GLCP */
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#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
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#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */
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#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
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#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */
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#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */
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#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */
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#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
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@ -59,176 +59,157 @@
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#define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */
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#define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */
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/* */
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/* GLIU*/
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/* */
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#define GLIU_SB_GLD_MSR_CAP (MSR_SB_GLIU + 0x00)
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/* GLIU */
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#define GLIU_SB_GLD_MSR_CAP (MSR_SB_GLIU + 0x00)
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#define GLIU_SB_GLD_MSR_CONF (MSR_SB_GLIU + 0x01)
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#define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04)
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#define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04)
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/* */
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/* USB1*/
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/* */
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#define USB1_SB_GLD_MSR_CAP (MSR_SB_USB1 + 0x00)
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/* USB1 */
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#define USB1_SB_GLD_MSR_CAP (MSR_SB_USB1 + 0x00)
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#define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01)
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#define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04)
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#define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04)
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/* */
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/* USB2*/
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/* */
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#define USB2_SB_GLD_MSR_CAP (MSR_SB_USB2 + 0x00)
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/* USB2 */
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#define USB2_SB_GLD_MSR_CAP (MSR_SB_USB2 + 0x00)
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#define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01)
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#define USB2_UPPER_SSDEN_SET (1 << 3 ) /* Bit 35 */
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#define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04)
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#define USB2_UPPER_SSDEN_SET (1 << 3 ) /* Bit 35 */
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#define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04)
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#define USB2_SB_GLD_MSR_DIAG (MSR_SB_USB2 + 0x05)
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#define USB2_SB_GLD_MSR_OHCI_BASE (MSR_SB_USB2 + 0x08)
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#define USB2_SB_GLD_MSR_EHCI_BASE (MSR_SB_USB2 + 0x09)
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#define USB2_SB_GLD_MSR_DEVCTL_BASE (MSR_SB_USB2 + 0x0A)
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#define USB2_SB_GLD_MSR_UOC_BASE (MSR_SB_USB2 + 0x0B) /* Option controller base */
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/* */
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/* ATA*/
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/* */
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/* ATA */
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#define ATA_SB_GLD_MSR_CAP (MSR_SB_ATA + 0x00)
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#define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01)
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#define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03)
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#define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04)
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#define ATA_SB_IDE_CFG (MSR_SB_ATA + 0x10)
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/* */
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/* AC97*/
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/* */
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/* AC97 */
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#define AC97_SB_GLD_MSR_CAP (MSR_SB_AC97 + 0x00)
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#define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01)
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#define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01)
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#define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04)
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/* */
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/* GLPCI*/
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/* */
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#define GLPCI_SB_GLD_MSR_CAP (MSR_SB_GLPCI + 0x00)
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#define GLPCI_SB_GLD_MSR_CONF (MSR_SB_GLPCI + 0x01)
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/* GLPCI */
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#define GLPCI_SB_GLD_MSR_CAP (MSR_SB_GLPCI + 0x00)
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#define GLPCI_SB_GLD_MSR_CONF (MSR_SB_GLPCI + 0x01)
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#define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04)
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#define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10)
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#define GLPCI_CRTL_PPIDE_SET (1 << 17)
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/* */
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/* GLCP*/
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/* */
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#define GLPCI_CRTL_PPIDE_SET (1 << 17)
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/* GLCP */
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#define GLCP_SB_GLD_MSR_CAP (MSR_SB_GLCP + 0x00)
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#define GLCP_SB_GLD_MSR_CONF (MSR_SB_GLCP + 0x01)
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#define GLCP_SB_GLD_MSR_CONF (MSR_SB_GLCP + 0x01)
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#define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04)
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#define GLCP_SB_CLKOFF (MSR_SB_GLCP + 0x10)
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/* */
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/* MDD*/
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/* */
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#define MDD_SB_GLD_MSR_CAP (MSR_SB_MDD + 0x00)
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#define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01)
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#define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04)
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#define LBAR_EN (0x01)
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#define IO_MASK (0x1f)
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#define MEM_MASK (0x0FFFFF)
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#define MDD_LBAR_IRQ (MSR_SB_MDD + 0x08)
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#define MDD_LBAR_KEL1 (MSR_SB_MDD + 0x09)
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#define MDD_LBAR_KEL2 (MSR_SB_MDD + 0x0A)
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#define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B)
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#define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C)
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#define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D)
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#define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E)
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#define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F)
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/* MDD */
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#define MDD_SB_GLD_MSR_CAP (MSR_SB_MDD + 0x00)
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#define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01)
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#define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04)
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#define LBAR_EN (0x01)
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#define IO_MASK (0x1f)
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#define MEM_MASK (0x0FFFFF)
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#define MDD_LBAR_IRQ (MSR_SB_MDD + 0x08)
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#define MDD_LBAR_KEL1 (MSR_SB_MDD + 0x09)
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#define MDD_LBAR_KEL2 (MSR_SB_MDD + 0x0A)
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#define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B)
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#define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C)
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#define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D)
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#define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E)
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#define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F)
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#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x010)
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#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x011)
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#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x012)
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#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x013)
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#define MDD_LEG_IO (MSR_SB_MDD + 0x014)
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#define MDD_PIN_OPT (MSR_SB_MDD + 0x015)
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#define MDD_SOFT_IRQ (MSR_SB_MDD + 0x016)
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#define MDD_SOFT_RESET (MSR_SB_MDD + 0x017)
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#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x018)
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#define MDD_NORF_T01 (MSR_SB_MDD + 0x019)
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#define MDD_NORF_T23 (MSR_SB_MDD + 0x01A)
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#define MDD_NANDF_DATA (MSR_SB_MDD + 0x01B)
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#define MDD_NADF_CNTL (MSR_SB_MDD + 0x01C)
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#define MDD_AC_DMA (MSR_SB_MDD + 0x01E)
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#define MDD_KEL_CNTRL (MSR_SB_MDD + 0x01F)
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#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x10)
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#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x11)
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#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x12)
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#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x13)
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#define MDD_LEG_IO (MSR_SB_MDD + 0x14)
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#define MDD_PIN_OPT (MSR_SB_MDD + 0x15)
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#define MDD_SOFT_IRQ (MSR_SB_MDD + 0x16)
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#define MDD_SOFT_RESET (MSR_SB_MDD + 0x17)
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#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x18)
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#define MDD_NORF_T01 (MSR_SB_MDD + 0x19)
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#define MDD_NORF_T23 (MSR_SB_MDD + 0x1A)
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#define MDD_NANDF_DATA (MSR_SB_MDD + 0x1B)
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#define MDD_NADF_CNTL (MSR_SB_MDD + 0x1C)
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#define MDD_AC_DMA (MSR_SB_MDD + 0x1E)
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#define MDD_KEL_CNTRL (MSR_SB_MDD + 0x1F)
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#define MDD_IRQM_YLOW (MSR_SB_MDD + 0x020)
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#define MDD_IRQM_YHIGH (MSR_SB_MDD + 0x021)
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#define MDD_IRQM_ZLOW (MSR_SB_MDD + 0x022)
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#define MDD_IRQM_ZHIGH (MSR_SB_MDD + 0x023)
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#define MDD_IRQM_PRIM (MSR_SB_MDD + 0x024)
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#define MDD_IRQM_LPC (MSR_SB_MDD + 0x025)
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#define MDD_IRQM_LXIRR (MSR_SB_MDD + 0x026)
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#define MDD_IRQM_HXIRR (MSR_SB_MDD + 0x027)
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#define MDD_IRQM_YLOW (MSR_SB_MDD + 0x20)
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#define MDD_IRQM_YHIGH (MSR_SB_MDD + 0x21)
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#define MDD_IRQM_ZLOW (MSR_SB_MDD + 0x22)
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#define MDD_IRQM_ZHIGH (MSR_SB_MDD + 0x23)
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#define MDD_IRQM_PRIM (MSR_SB_MDD + 0x24)
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#define MDD_IRQM_LPC (MSR_SB_MDD + 0x25)
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#define MDD_IRQM_LXIRR (MSR_SB_MDD + 0x26)
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#define MDD_IRQM_HXIRR (MSR_SB_MDD + 0x27)
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#define MDD_MFGPT_IRQ (MSR_SB_MDD + 0x028)
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#define MDD_MFGPT_NR (MSR_SB_MDD + 0x029)
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#define MDD_MFGPT_RES0 (MSR_SB_MDD + 0x02A)
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#define MDD_MFGPT_RES1 (MSR_SB_MDD + 0x02B)
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#define MDD_MFGPT_IRQ (MSR_SB_MDD + 0x28)
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#define MDD_MFGPT_NR (MSR_SB_MDD + 0x29)
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#define MDD_MFGPT_RES0 (MSR_SB_MDD + 0x2A)
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#define MDD_MFGPT_RES1 (MSR_SB_MDD + 0x2B)
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#define MDD_FLOP_S3F2 (MSR_SB_MDD + 0x030)
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#define MDD_FLOP_S3F7 (MSR_SB_MDD + 0x031)
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#define MDD_FLOP_S372 (MSR_SB_MDD + 0x032)
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#define MDD_FLOP_S377 (MSR_SB_MDD + 0x033)
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#define MDD_FLOP_S3F2 (MSR_SB_MDD + 0x30)
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#define MDD_FLOP_S3F7 (MSR_SB_MDD + 0x31)
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#define MDD_FLOP_S372 (MSR_SB_MDD + 0x32)
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#define MDD_FLOP_S377 (MSR_SB_MDD + 0x33)
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#define MDD_PIC_S (MSR_SB_MDD + 0x034)
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#define MDD_PIT_S (MSR_SB_MDD + 0x036)
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#define MDD_PIT_CNTRL (MSR_SB_MDD + 0x037)
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#define MDD_PIC_S (MSR_SB_MDD + 0x34)
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#define MDD_PIT_S (MSR_SB_MDD + 0x36)
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#define MDD_PIT_CNTRL (MSR_SB_MDD + 0x37)
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#define MDD_UART1_MOD (MSR_SB_MDD + 0x038)
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#define MDD_UART1_DON (MSR_SB_MDD + 0x039)
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#define MDD_UART1_CONF (MSR_SB_MDD + 0x03A)
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#define MDD_UART2_MOD (MSR_SB_MDD + 0x03C)
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#define MDD_UART2_DON (MSR_SB_MDD + 0x03D)
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#define MDD_UART2_CONF (MSR_SB_MDD + 0x03E)
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#define MDD_UART1_MOD (MSR_SB_MDD + 0x38)
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#define MDD_UART1_DON (MSR_SB_MDD + 0x39)
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#define MDD_UART1_CONF (MSR_SB_MDD + 0x3A)
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#define MDD_UART2_MOD (MSR_SB_MDD + 0x3C)
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#define MDD_UART2_DON (MSR_SB_MDD + 0x3D)
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#define MDD_UART2_CONF (MSR_SB_MDD + 0x3E)
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#define MDD_DMA_MAP (MSR_SB_MDD + 0x040)
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#define MDD_DMA_SHAD1 (MSR_SB_MDD + 0x041)
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#define MDD_DMA_SHAD2 (MSR_SB_MDD + 0x042)
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#define MDD_DMA_SHAD3 (MSR_SB_MDD + 0x043)
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#define MDD_DMA_SHAD4 (MSR_SB_MDD + 0x044)
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#define MDD_DMA_SHAD5 (MSR_SB_MDD + 0x045)
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#define MDD_DMA_SHAD6 (MSR_SB_MDD + 0x046)
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#define MDD_DMA_SHAD7 (MSR_SB_MDD + 0x047)
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#define MDD_DMA_SHAD8 (MSR_SB_MDD + 0x048)
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#define MDD_DMA_SHAD9 (MSR_SB_MDD + 0x049)
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#define MDD_DMA_MAP (MSR_SB_MDD + 0x40)
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#define MDD_DMA_SHAD1 (MSR_SB_MDD + 0x41)
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#define MDD_DMA_SHAD2 (MSR_SB_MDD + 0x42)
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#define MDD_DMA_SHAD3 (MSR_SB_MDD + 0x43)
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#define MDD_DMA_SHAD4 (MSR_SB_MDD + 0x44)
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#define MDD_DMA_SHAD5 (MSR_SB_MDD + 0x45)
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#define MDD_DMA_SHAD6 (MSR_SB_MDD + 0x46)
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#define MDD_DMA_SHAD7 (MSR_SB_MDD + 0x47)
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#define MDD_DMA_SHAD8 (MSR_SB_MDD + 0x48)
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#define MDD_DMA_SHAD9 (MSR_SB_MDD + 0x49)
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#define MDD_LPC_EADDR (MSR_SB_MDD + 0x04C)
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#define MDD_LPC_ESTAT (MSR_SB_MDD + 0x04D)
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#define MDD_LPC_SIRQ (MSR_SB_MDD + 0x04E)
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#define MDD_LPC_RES (MSR_SB_MDD + 0x04F)
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#define MDD_LPC_EADDR (MSR_SB_MDD + 0x4C)
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#define MDD_LPC_ESTAT (MSR_SB_MDD + 0x4D)
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#define MDD_LPC_SIRQ (MSR_SB_MDD + 0x4E)
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#define MDD_LPC_RES (MSR_SB_MDD + 0x4F)
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#define MDD_PML_TMR (MSR_SB_MDD + 0x050)
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#define MDD_RTC_RAM_LO_CK (MSR_SB_MDD + 0x054)
|
||||
#define MDD_RTC_DOMA_IND (MSR_SB_MDD + 0x055)
|
||||
#define MDD_RTC_MONA_IND (MSR_SB_MDD + 0x056)
|
||||
#define MDD_RTC_CENTURY_OFFSET (MSR_SB_MDD + 0x057)
|
||||
#define MDD_PML_TMR (MSR_SB_MDD + 0x50)
|
||||
#define MDD_RTC_RAM_LO_CK (MSR_SB_MDD + 0x54)
|
||||
#define MDD_RTC_DOMA_IND (MSR_SB_MDD + 0x55)
|
||||
#define MDD_RTC_MONA_IND (MSR_SB_MDD + 0x56)
|
||||
#define MDD_RTC_CENTURY_OFFSET (MSR_SB_MDD + 0x57)
|
||||
|
||||
/* ***********************************************************/
|
||||
/* LBUS Device Equates - */
|
||||
/* ***********************************************************/
|
||||
|
||||
/* */
|
||||
/* SMBus*/
|
||||
/* */
|
||||
/* LBUS Device Equates - */
|
||||
|
||||
/* SMBus */
|
||||
#define SMB_SDA 0x00
|
||||
#define SMB_STS 0x01
|
||||
#define SMB_STS_SLVSTP (0x01 << 7)
|
||||
#define SMB_STS_SDAST (0x01 << 6)
|
||||
#define SMB_STS_SLVSTP (0x01 << 7)
|
||||
#define SMB_STS_SDAST (0x01 << 6)
|
||||
#define SMB_STS_BER (0x01 << 5)
|
||||
#define SMB_STS_NEGACK (0x01 << 4)
|
||||
#define SMB_STS_STASTR (0x01 << 3)
|
||||
#define SMB_STS_NMATCH (0x01 << 2)
|
||||
#define SMB_STS_MASTER (0x01 << 1)
|
||||
#define SMB_STS_XMIT (0x01 << 0)
|
||||
#define SMB_STS_NEGACK (0x01 << 4)
|
||||
#define SMB_STS_STASTR (0x01 << 3)
|
||||
#define SMB_STS_NMATCH (0x01 << 2)
|
||||
#define SMB_STS_MASTER (0x01 << 1)
|
||||
#define SMB_STS_XMIT (0x01 << 0)
|
||||
|
||||
#define SMB_CTRL_STS 0x02
|
||||
#define SMB_CSTS_TGSCL (0x01 << 5)
|
||||
#define SMB_CSTS_TSDA (0x01 << 4)
|
||||
#define SMB_CSTS_GCMTCH (0x01 << 3)
|
||||
#define SMB_CSTS_MATCH (0x01 << 2)
|
||||
#define SMB_CSTS_TGSCL (0x01 << 5)
|
||||
#define SMB_CSTS_TSDA (0x01 << 4)
|
||||
#define SMB_CSTS_GCMTCH (0x01 << 3)
|
||||
#define SMB_CSTS_MATCH (0x01 << 2)
|
||||
#define SMB_CSTS_BB (0x01 << 1)
|
||||
#define SMB_CSTS_BUSY (0x01 << 0)
|
||||
#define SMB_CSTS_BUSY (0x01 << 0)
|
||||
|
||||
#define SMB_CTRL1 0x03
|
||||
#define SMB_CTRL1_STASTRE (0x01 << 7)
|
||||
|
|
@ -248,20 +229,17 @@
|
|||
|
||||
#define SMB_CTRL3 0x06
|
||||
|
||||
/* */
|
||||
/* GPIO*/
|
||||
/* */
|
||||
|
||||
#define GPIOL_0_SET (1 << 0)
|
||||
#define GPIOL_1_SET (1 << 1)
|
||||
#define GPIOL_2_SET (1 << 2)
|
||||
#define GPIOL_3_SET (1 << 3)
|
||||
#define GPIOL_4_SET (1 << 4)
|
||||
#define GPIOL_5_SET (1 << 5)
|
||||
#define GPIOL_6_SET (1 << 6)
|
||||
#define GPIOL_7_SET (1 << 7)
|
||||
#define GPIOL_8_SET (1 << 8)
|
||||
#define GPIOL_9_SET (1 << 9)
|
||||
/* GPIO */
|
||||
#define GPIOL_0_SET (1 << 0)
|
||||
#define GPIOL_1_SET (1 << 1)
|
||||
#define GPIOL_2_SET (1 << 2)
|
||||
#define GPIOL_3_SET (1 << 3)
|
||||
#define GPIOL_4_SET (1 << 4)
|
||||
#define GPIOL_5_SET (1 << 5)
|
||||
#define GPIOL_6_SET (1 << 6)
|
||||
#define GPIOL_7_SET (1 << 7)
|
||||
#define GPIOL_8_SET (1 << 8)
|
||||
#define GPIOL_9_SET (1 << 9)
|
||||
#define GPIOL_10_SET (1 << 10)
|
||||
#define GPIOL_11_SET (1 << 11)
|
||||
#define GPIOL_12_SET (1 << 12)
|
||||
|
|
@ -320,103 +298,103 @@
|
|||
#define GPIOH_30_CLEAR (1 << 30)
|
||||
#define GPIOH_31_CLEAR (1 << 31)
|
||||
|
||||
/* GPIO LOW Bank Bit Registers*/
|
||||
#define GPIOL_OUTPUT_VALUE (0x00)
|
||||
#define GPIOL_OUTPUT_ENABLE (0x04)
|
||||
#define GPIOL_OUT_OPENDRAIN (0x08)
|
||||
/* GPIO LOW Bank Bit Registers */
|
||||
#define GPIOL_OUTPUT_VALUE (0x00)
|
||||
#define GPIOL_OUTPUT_ENABLE (0x04)
|
||||
#define GPIOL_OUT_OPENDRAIN (0x08)
|
||||
#define GPIOL_OUTPUT_INVERT_ENABLE (0x0C)
|
||||
#define GPIOL_OUT_AUX1_SELECT (0x10)
|
||||
#define GPIOL_OUT_AUX2_SELECT (0x14)
|
||||
#define GPIOL_PULLUP_ENABLE (0x18)
|
||||
#define GPIOL_PULLUP_ENABLE (0x18)
|
||||
#define GPIOL_PULLDOWN_ENABLE (0x1C)
|
||||
#define GPIOL_INPUT_ENABLE (0x20)
|
||||
#define GPIOL_INPUT_ENABLE (0x20)
|
||||
#define GPIOL_INPUT_INVERT_ENABLE (0x24)
|
||||
#define GPIOL_IN_FILTER_ENABLE (0x28)
|
||||
#define GPIOL_IN_EVENTCOUNT_ENABLE (0x2C)
|
||||
#define GPIOL_READ_BACK (0x30)
|
||||
#define GPIOL_READ_BACK (0x30)
|
||||
#define GPIOL_IN_AUX1_SELECT (0x34)
|
||||
#define GPIOL_EVENTS_ENABLE (0x38)
|
||||
#define GPIOL_LOCK_ENABLE (0x3C)
|
||||
#define GPIOL_EVENTS_ENABLE (0x38)
|
||||
#define GPIOL_LOCK_ENABLE (0x3C)
|
||||
#define GPIOL_IN_POSEDGE_ENABLE (0x40)
|
||||
#define GPIOL_IN_NEGEDGE_ENABLE (0x44)
|
||||
#define GPIOL_IN_POSEDGE_STATUS (0x48)
|
||||
#define GPIOL_IN_NEGEDGE_STATUS (0x4C)
|
||||
|
||||
/* GPIO High Bank Bit Registers*/
|
||||
#define GPIOH_OUTPUT_VALUE (0x80)
|
||||
#define GPIOH_OUTPUT_ENABLE (0x84)
|
||||
#define GPIOH_OUT_OPENDRAIN (0x88)
|
||||
/* GPIO High Bank Bit Registers */
|
||||
#define GPIOH_OUTPUT_VALUE (0x80)
|
||||
#define GPIOH_OUTPUT_ENABLE (0x84)
|
||||
#define GPIOH_OUT_OPENDRAIN (0x88)
|
||||
#define GPIOH_OUTPUT_INVERT_ENABLE (0x8C)
|
||||
#define GPIOH_OUT_AUX1_SELECT (0x90)
|
||||
#define GPIOH_OUT_AUX2_SELECT (0x94)
|
||||
#define GPIOH_PULLUP_ENABLE (0x98)
|
||||
#define GPIOH_PULLUP_ENABLE (0x98)
|
||||
#define GPIOH_PULLDOWN_ENABLE (0x9C)
|
||||
#define GPIOH_INPUT_ENABLE (0x0A0)
|
||||
#define GPIOH_INPUT_INVERT_ENABLE (0x0A4)
|
||||
#define GPIOH_IN_FILTER_ENABLE (0x0A8)
|
||||
#define GPIOH_IN_EVENTCOUNT_ENABLE (0x0AC)
|
||||
#define GPIOH_READ_BACK (0x0B0)
|
||||
#define GPIOH_IN_AUX1_SELECT (0x0B4)
|
||||
#define GPIOH_EVENTS_ENABLE (0x0B8)
|
||||
#define GPIOH_LOCK_ENABLE (0x0BC)
|
||||
#define GPIOH_IN_POSEDGE_ENABLE (0x0C0)
|
||||
#define GPIOH_IN_NEGEDGE_ENABLE (0x0C4)
|
||||
#define GPIOH_IN_POSEDGE_STATUS (0x0C8)
|
||||
#define GPIOH_IN_NEGEDGE_STATUS (0x0CC)
|
||||
#define GPIOH_INPUT_ENABLE (0xA0)
|
||||
#define GPIOH_INPUT_INVERT_ENABLE (0xA4)
|
||||
#define GPIOH_IN_FILTER_ENABLE (0xA8)
|
||||
#define GPIOH_IN_EVENTCOUNT_ENABLE (0xAC)
|
||||
#define GPIOH_READ_BACK (0xB0)
|
||||
#define GPIOH_IN_AUX1_SELECT (0xB4)
|
||||
#define GPIOH_EVENTS_ENABLE (0xB8)
|
||||
#define GPIOH_LOCK_ENABLE (0xBC)
|
||||
#define GPIOH_IN_POSEDGE_ENABLE (0xC0)
|
||||
#define GPIOH_IN_NEGEDGE_ENABLE (0xC4)
|
||||
#define GPIOH_IN_POSEDGE_STATUS (0xC8)
|
||||
#define GPIOH_IN_NEGEDGE_STATUS (0xCC)
|
||||
|
||||
/* Input Conditioning Function Registers*/
|
||||
/* Input Conditioning Function Registers */
|
||||
#define GPIO_00_FILTER_AMOUNT (0x50)
|
||||
#define GPIO_00_FILTER_COUNT (0x52)
|
||||
#define GPIO_00_EVENT_COUNT (0x54)
|
||||
#define GPIO_00_EVENT_COUNT (0x54)
|
||||
#define GPIO_00_EVENTCOMPARE_VALUE (0x56)
|
||||
#define GPIO_01_FILTER_AMOUNT (0x58)
|
||||
#define GPIO_01_FILTER_COUNT (0x5A)
|
||||
#define GPIO_01_EVENT_COUNT (0x5C)
|
||||
#define GPIO_01_EVENT_COUNT (0x5C)
|
||||
#define GPIO_01_EVENTCOMPARE_VALUE (0x5E)
|
||||
#define GPIO_02_FILTER_AMOUNT (0x60)
|
||||
#define GPIO_02_FILTER_COUNT (0x62)
|
||||
#define GPIO_02_EVENT_COUNT (0x64)
|
||||
#define GPIO_02_EVENT_COUNT (0x64)
|
||||
#define GPIO_02_EVENTCOMPARE_VALUE (0x66)
|
||||
#define GPIO_03_FILTER_AMOUNT (0x68)
|
||||
#define GPIO_03_FILTER_COUNT (0x6A)
|
||||
#define GPIO_03_EVENT_COUNT (0x6C)
|
||||
#define GPIO_03_EVENT_COUNT (0x6C)
|
||||
#define GPIO_03_EVENTCOMPARE_VALUE (0x6E)
|
||||
#define GPIO_04_FILTER_AMOUNT (0x70)
|
||||
#define GPIO_04_FILTER_COUNT (0x72)
|
||||
#define GPIO_04_EVENT_COUNT (0x74)
|
||||
#define GPIO_04_EVENT_COUNT (0x74)
|
||||
#define GPIO_04_EVENTCOMPARE_VALUE (0x76)
|
||||
#define GPIO_05_FILTER_AMOUNT (0x78)
|
||||
#define GPIO_05_FILTER_COUNT (0x7A)
|
||||
#define GPIO_05_EVENT_COUNT (0x7C)
|
||||
#define GPIO_05_EVENT_COUNT (0x7C)
|
||||
#define GPIO_05_EVENTCOMPARE_VALUE (0x7E)
|
||||
#define GPIO_06_FILTER_AMOUNT (0x0D0)
|
||||
#define GPIO_06_FILTER_COUNT (0x0D2)
|
||||
#define GPIO_06_EVENT_COUNT (0x0D4)
|
||||
#define GPIO_06_EVENTCOMPARE_VALUE (0x0D6)
|
||||
#define GPIO_07_FILTER_AMOUNT (0x0D8)
|
||||
#define GPIO_07_FILTER_COUNT (0x0DA)
|
||||
#define GPIO_07_EVENT_COUNT (0x0DC)
|
||||
#define GPIO_07_EVENTCOMPARE_VALUE (0x0DE)
|
||||
#define GPIO_06_FILTER_AMOUNT (0xD0)
|
||||
#define GPIO_06_FILTER_COUNT (0xD2)
|
||||
#define GPIO_06_EVENT_COUNT (0xD4)
|
||||
#define GPIO_06_EVENTCOMPARE_VALUE (0xD6)
|
||||
#define GPIO_07_FILTER_AMOUNT (0xD8)
|
||||
#define GPIO_07_FILTER_COUNT (0xDA)
|
||||
#define GPIO_07_EVENT_COUNT (0xDC)
|
||||
#define GPIO_07_EVENTCOMPARE_VALUE (0xDE)
|
||||
|
||||
/* R/W GPIO Interrupt &PME Mapper Registers*/
|
||||
#define GPIO_MAPPER_X (0x0E0)
|
||||
#define GPIO_MAPPER_Y (0x0E4)
|
||||
#define GPIO_MAPPER_Z (0x0E8)
|
||||
#define GPIO_MAPPER_W (0x0EC)
|
||||
#define GPIO_FE_SELECT_0 (0x0F0)
|
||||
#define GPIO_FE_SELECT_1 (0x0F1)
|
||||
#define GPIO_FE_SELECT_2 (0x0F2)
|
||||
#define GPIO_FE_SELECT_3 (0x0F3)
|
||||
#define GPIO_FE_SELECT_4 (0x0F4)
|
||||
#define GPIO_FE_SELECT_5 (0x0F5)
|
||||
#define GPIO_FE_SELECT_6 (0x0F6)
|
||||
#define GPIO_FE_SELECT_7 (0x0F7)
|
||||
/* R/W GPIO Interrupt &PME Mapper Registers */
|
||||
#define GPIO_MAPPER_X (0xE0)
|
||||
#define GPIO_MAPPER_Y (0xE4)
|
||||
#define GPIO_MAPPER_Z (0xE8)
|
||||
#define GPIO_MAPPER_W (0xEC)
|
||||
#define GPIO_FE_SELECT_0 (0xF0)
|
||||
#define GPIO_FE_SELECT_1 (0xF1)
|
||||
#define GPIO_FE_SELECT_2 (0xF2)
|
||||
#define GPIO_FE_SELECT_3 (0xF3)
|
||||
#define GPIO_FE_SELECT_4 (0xF4)
|
||||
#define GPIO_FE_SELECT_5 (0xF5)
|
||||
#define GPIO_FE_SELECT_6 (0xF6)
|
||||
#define GPIO_FE_SELECT_7 (0xF7)
|
||||
|
||||
/* Event Counter Decrement Registers*/
|
||||
#define GPIOL_IN_EVENT_DECREMENT (0x0F8)
|
||||
#define GPIOH_IN_EVENT_DECREMENT (0x0FC)
|
||||
/* Event Counter Decrement Registers */
|
||||
#define GPIOL_IN_EVENT_DECREMENT (0xF8)
|
||||
#define GPIOH_IN_EVENT_DECREMENT (0xFC)
|
||||
|
||||
/* PMC register*/
|
||||
/* PMC register */
|
||||
#define PM_SSD (0x00)
|
||||
#define PM_SCXA (0x04)
|
||||
#define PM_SCYA (0x08)
|
||||
|
|
@ -438,12 +416,12 @@
|
|||
#define PM_SSC (0x54)
|
||||
|
||||
/* FLASH device macros */
|
||||
#define FLASH_TYPE_NONE 0 /* No flash device installed */
|
||||
#define FLASH_TYPE_NAND 1 /* NAND device */
|
||||
#define FLASH_TYPE_NOR 2 /* NOR device */
|
||||
#define FLASH_TYPE_NONE 0 /* No flash device installed */
|
||||
#define FLASH_TYPE_NAND 1 /* NAND device */
|
||||
#define FLASH_TYPE_NOR 2 /* NOR device */
|
||||
|
||||
#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */
|
||||
#define FLASH_IF_IO 2 /* I/O interface for Flash device */
|
||||
#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */
|
||||
#define FLASH_IF_IO 2 /* I/O interface for Flash device */
|
||||
|
||||
/* Flash Memory Mask values */
|
||||
#define FLASH_MEM_DEFAULT 0x00000000
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
/*
|
||||
* cs5536_early_setup.c: Early chipset initialization for CS5536 companion device
|
||||
* This file implements the initialization sequence documented in section 4.2 of
|
||||
* AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide.
|
||||
* AMD Geode GX Processor CS5536 Companion Device GeodeROM Porting Guide.
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in New Issue