diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 0108116666..f42456413b 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -46,7 +46,7 @@ void init_iommu()
 	MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */
 
 	/* clear GTT */
-	u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
+	u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC);
 	if (gtt & 0x400) { /* VT mode */
 		pci_devfn_t igd = PCI_DEV(0, 2, 0);
 
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 7de2c73fc9..a38874a563 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -685,7 +685,7 @@ static void i945_setup_pci_express_x16(void)
 	if (reg32 == 0x030000) {
 		printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n");
 		reg16 = (1 << 1);
-		pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16);
+		pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16);
 
 		reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN);
 		reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1);
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index eb67c65990..e075ac136c 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -98,7 +98,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
 
 	gtt_setup(mmio);
 
-	pci_write_config16(vga, 0x52, 0x130);
+	pci_write_config16(vga, GGC, 0x130);
 
 	/* Disable VGA.  */
 	write32(mmio + VGACNTRL, VGA_DISP_DISABLE);