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soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree 

This patch adds the support for CmdTriStateDis FSP upd in skylake
soc structure so that we can define it in devicetree.CmdTriStateDis
needed to be set for the skylake/kabylake based boards where LPDDR3
design is without RTT for CMD/CTRL.We need to set this bit for those
designs for the margin to be proper.

BUG=b:111812662
TEST=Run memtester app and also webgl fishtank on
     the LPDDR3 kabylake boards and also check the
     margin data is proper in FSP.

Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/28424
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shaunak Saha 2018-08-31 12:49:08 -07:00 committed by Patrick Georgi
parent f47ccbdd47
commit ef250c47e4
2 changed files with 4 additions and 0 deletions
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3
src/soc/intel/skylake/chip.h
View File

@ -154,6 +154,9 @@ struct soc_intel_skylake_config {
/* Enable/disable Rank Margin Tool */ /* Enable/disable Rank Margin Tool */
u8 Rmt; u8 Rmt;
/* Disable Command TriState */
u8 CmdTriStateDis;
/* Lan */ /* Lan */
u8 EnableLan; u8 EnableLan;
u8 EnableLanLtr; u8 EnableLanLtr;

1
src/soc/intel/skylake/romstage/romstage_fsp20.c
View File

@ -224,6 +224,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->SaGv = config->SaGv; m_cfg->SaGv = config->SaGv;
m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
m_cfg->RMT = config->Rmt; m_cfg->RMT = config->Rmt;
m_cfg->CmdTriStateDis = config->CmdTriStateDis;
m_cfg->DdrFreqLimit = config->DdrFreqLimit; m_cfg->DdrFreqLimit = config->DdrFreqLimit;
m_cfg->VmxEnable = config->VmxEnable; m_cfg->VmxEnable = config->VmxEnable;
m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->PrmrrSize = config->PrmrrSize;