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mb/google/dedede/var/beadrix: Update SoC gpio pin of BC1.2 

Update SoC GPIO setting of adding BC1.2 SLGC55545 according to beadrix
schematics.

GPP_A18 : NC -> NF1 (USB_OC0_N)

BUG=b:214393595, b:226294980
BRANCH=None
TEST=on beadrix, validated by beadrix's Type A working properly.

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I746931582cc12f49f7f1c667563350ebac8ddfa1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Teddy Shih 2022-06-24 12:36:06 +08:00 committed by Karthik Ramasubramanian
parent ec1afc58af
commit ef29befb09
2 changed files with 3 additions and 0 deletions
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2
src/mainboard/google/dedede/variants/beadrix/gpio.c
View File

@ -11,6 +11,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_A10, 1, PWROK),
/* A11 : TOUCH_RPT_EN ==> NC */
PAD_NC(GPP_A11, NONE),
/* A18 : USB_OC0_N */
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
/* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL */
PAD_CFG_GPO(GPP_B7, 1, DEEP),

1
src/mainboard/google/dedede/variants/beadrix/overridetree.cb
View File

@ -9,6 +9,7 @@ end
chip soc/intel/jasperlake
# USB Port Configuration
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB3 Type A port
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable unused USB2P_5 and USB2N_5
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable unused USB2P_7 and USB2N_7