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rockchip: rk3399: enable pwm 

Reuse the rockchip common pwm driver.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I1a1ab237f891f06affb74817b5cae1a034a9760e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 37afce0f94435ffef8bdd74b4251430f11ec22f4
Original-Change-Id: Ia94985f56e424d049fdcc5be86c696577d52a07c
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/333255
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14714
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Lin Huang 2016-03-23 19:35:46 +08:00 committed by Patrick Georgi
parent 92c2f5e38b
commit ef2eb9df6c
3 changed files with 4 additions and 0 deletions
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1
src/soc/rockchip/rk3399/Makefile.inc
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@ -41,6 +41,7 @@ romstage-y += ../common/spi.c
romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
romstage-y += clock.c romstage-y += clock.c
romstage-y += mmu_operations.c romstage-y += mmu_operations.c
romstage-y += ../common/pwm.c
romstage-y += timer.c romstage-y += timer.c
romstage-y += romstage.c romstage-y += romstage.c

1
src/soc/rockchip/rk3399/include/soc/addressmap.h
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@ -56,6 +56,7 @@
#define TSADC_BASE 0xff260000 #define TSADC_BASE 0xff260000
#define SARADC_BASE 0xff100000 #define SARADC_BASE 0xff100000
#define RK_PWM_BASE 0xff420000
#define IC_BASES { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, \ #define IC_BASES { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, \
I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE } I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE }

2
src/soc/rockchip/rk3399/include/soc/clock.h
View File

@ -95,6 +95,8 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE;
#define PERILP1_HCLK_HZ (99000*KHz) #define PERILP1_HCLK_HZ (99000*KHz)
#define PERILP1_PCLK_HZ (49500*KHz) #define PERILP1_PCLK_HZ (49500*KHz)
#define PWM_CLOCK_HZ PMU_PCLK_HZ
enum apll_l_frequencies { enum apll_l_frequencies {
APLL_L_1600_MHZ, APLL_L_1600_MHZ,
APLL_L_600_MHZ, APLL_L_600_MHZ,