vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v3162
The FSP-M/S/T related headers added are generated as per FSP v3162. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ie6e6db704bcf86034fc9a3423101f0391ba2327e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54869 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tan, Lean Sheng
Werner Zeh
parent
29ad904cbe
commit
ef41e8a44c
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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@ -990,7 +990,7 @@ typedef struct {
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UINT8 OcSupport;
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/** Offset 0x026F - Over clocking Lock
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Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable.
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Over clocking Lock Enable/Disable; 0: Disable; <b>1: Enable</b>
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$EN_DIS
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**/
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UINT8 OcLock;
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@ -2927,71 +2927,87 @@ typedef struct {
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Tcc (Time Coordinated Computing) Tuning Enabled
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$EN_DIS
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**/
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UINT8 TccTuningEnable;
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UINT8 TccTuningEnablePreMem;
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/** Offset 0x06BE
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**/
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UINT8 UnusedUpdSpace22[2];
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/** Offset 0x06C0 - Tcc Register File Base Address
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Tcc (Time Coordinated Computing) Register File Base Address
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/** Offset 0x06C0 - Tcc Buffer Config File Base Address
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Tcc (Time Coordinated Computing) Buffer Config File File Base Address
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**/
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UINT32 TccConfigBase;
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UINT32 TccBufferCfgBase;
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/** Offset 0x06C4 - Tcc Register File Size
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Tcc (Time Coordinated Computing) Register File Size
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/** Offset 0x06C4 - Tcc Buffer Config File Size
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Tcc (Time Coordinated Computing) Buffer Config File Size
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**/
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UINT32 TccConfigSize;
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UINT32 TccBufferCfgSize;
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/** Offset 0x06C8 - Force ME DID Init Status
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/** Offset 0x06C8 - Tcc BIOS Config File Base Address
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Tcc (Time Coordinated Computing) TCC BIOS Config File Base Address
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**/
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UINT32 TccStreamCfgBasePreMem;
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/** Offset 0x06CC - Tcc BIOS Config File Size
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Tcc (Time Coordinated Computing) TCC BIOS Config File Size
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**/
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UINT32 TccStreamCfgSizePreMem;
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/** Offset 0x06D0 - Force ME DID Init Status
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Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
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ME DID init stat value
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$EN_DIS
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**/
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UINT8 DidInitStat;
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/** Offset 0x06C9 - CPU Replaced Polling Disable
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/** Offset 0x06D1 - CPU Replaced Polling Disable
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Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
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$EN_DIS
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**/
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UINT8 DisableCpuReplacedPolling;
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/** Offset 0x06CA - ME DID Message
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/** Offset 0x06D2 - ME DID Message
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Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent
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the DID message from being sent)
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$EN_DIS
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**/
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UINT8 SendDidMsg;
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/** Offset 0x06CB - Check HECI message before send
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/** Offset 0x06D3 - Check HECI message before send
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Test, 0: disable, 1: enable, Enable/Disable message check.
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$EN_DIS
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**/
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UINT8 DisableMessageCheck;
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/** Offset 0x06CC - Skip MBP HOB
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/** Offset 0x06D4 - Skip MBP HOB
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Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
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$EN_DIS
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**/
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UINT8 SkipMbpHob;
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/** Offset 0x06CD - HECI2 Interface Communication
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/** Offset 0x06D5 - HECI2 Interface Communication
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Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
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$EN_DIS
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**/
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UINT8 HeciCommunication2;
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/** Offset 0x06CE - Enable KT device
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/** Offset 0x06D6 - Enable KT device
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Test, 0: disable, 1: enable, Enable or Disable KT device.
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$EN_DIS
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**/
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UINT8 KtDeviceEnable;
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/** Offset 0x06CF
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/** Offset 0x06D7 - Skip CPU replacement check
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Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
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$EN_DIS
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**/
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UINT8 UnusedUpdSpace23[5];
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UINT8 SkipCpuReplacementCheck;
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/** Offset 0x06D4
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/** Offset 0x06D8
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**/
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UINT8 UnusedUpdSpace23[4];
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/** Offset 0x06DC
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**/
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UINT8 ReservedFspmUpd2[20];
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} FSP_M_CONFIG;
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@ -3012,11 +3028,11 @@ typedef struct {
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**/
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FSP_M_CONFIG FspmConfig;
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/** Offset 0x06E8
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/** Offset 0x06F0
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**/
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UINT8 UnusedUpdSpace24[6];
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/** Offset 0x06EE
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/** Offset 0x06F6
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**/
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UINT16 UpdTerminator;
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} FSPM_UPD;
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File diff suppressed because it is too large
Load Diff
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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