Documentation: Add Montevina ThinkPads common page
- Add a common page about Montevina ThinkPads. - Describe how to disable ME and remove its firmware on these models. - Describe vendor flash layouts. Thanks to swiftgeek for his help when writing this, especially the last paragraph and flash layouts. Change-Id: I85917821efe63fff4b933b6226e99c17b63eb1b9 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Evgeny Zinoviev
Patrick Georgi
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@ -77,6 +77,7 @@ The boards in this section are not real mainboards, but emulators.
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### GM45 series
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- [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md)
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- [X301](lenovo/x301.md)
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### Sandy Bridge series
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@ -0,0 +1,164 @@
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# Lenovo X200 / T400 / T500 / X301 common
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These models are sold with either 8 MiB or 4 MiB flash chip. You can identify
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the chip in your machine through flashrom:
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```console
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# flashrom -p internal
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```
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Note that this does not allow you to determine whether the chip is in a SOIC-8
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or a SOIC-16 package.
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## Installing without ME firmware
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```eval_rst
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.. Note::
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**ThinkPad R500** has slightly different flash layout (it doesn't have
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``gbe`` region), so the process would be a little different for that model.
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```
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On Montevina machines it's possible to disable ME and remove its firmware from
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SPI flash by modifying the flash descriptor. This also makes it possible to use
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the flash region the ME used for `bios` region, allowing for much larger
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payloads.
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First of all create a backup of your ROM with an external programmer:
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```console
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# flashrom -p YOUR_PROGRAMMER -r backup.rom
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```
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Then, split the IFD regions into separate filse with ifdtool. You will need
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`flashregion_3_gbe.bin` later.
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```console
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$ ifdtool -x backup.rom
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```
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Now you need to patch the flash descriptor. You can either [modify the one from
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your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or
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[generate a completely new one with **bincfg**](#creating-a-new-flash-descriptor-using-bincfg).
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#### Modifying flash descriptor using ifdtool
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Pick the layout according to your chip size from the table below and save it to
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the `new_layout.txt` file:
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```eval_rst
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+---------------------------+---------------------------+---------------------------+
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| 4 MB chip | 8 MB chip | 16 MB chip |
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+===========================+===========================+===========================+
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| .. code-block:: none | .. code-block:: none | .. code-block:: none |
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| | | |
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| 00000000:00000fff fd | 00000000:00000fff fd | 00000000:00000fff fd |
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| 00001000:00002fff gbe | 00001000:00002fff gbe | 00001000:00002fff gbe |
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| 00003000:003fffff bios | 00003000:007fffff bios | 00003000:01ffffff bios |
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| 00fff000:00000fff pd | 00fff000:00000fff pd | 00fff000:00000fff pd |
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| 00fff000:00000fff me | 00fff000:00000fff me | 00fff000:00000fff me |
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+---------------------------+---------------------------+---------------------------+
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```
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The last two lines define `pd` and `me` regions of negative size. This way
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ifdtool will mark those as unused.
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Update regions in the flash descrpitor (it was extracted previously with
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`ifdtool -x`):
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```console
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$ ifdtool -n new_layout.txt flashregion_0_flashdescriptor.bin
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```
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Set `MeDisable` bit in ICH0 and MCH0 straps:
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```console
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$ ifdtool -M 1 flashregion_0_flashdescriptor.bin.new
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```
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Delete previous descriptors and rename the final one:
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```console
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$ rm flashregion_0_flashdescriptor.bin
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$ rm flashregion_0_flashdescriptor.bin.new
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$ mv flashregion_0_flashdescriptor.bin.new.new flashregion_0_flashdescriptor.bin
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```
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Continue to the [Configuring coreboot](#configuring-coreboot) section.
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#### Creating a new flash descriptor using bincfg
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There is a tool to generate a modified flash descriptor called **bincfg**. Go to
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`util/bincfg` and build it:
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```console
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$ cd util/bincfg
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$ make
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```
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If your flash is not 8 MB, you need to change values of `flcomp_density1` and
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`flreg1_limit` in the ifd-x200.set file according to following table:
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```eval_rst
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+-----------------+-------+-------+--------+
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| | 4 MB | 8 MB | 16 MB |
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+=================+=======+=======+========+
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| flcomp_density1 | 0x3 | 0x4 | 0x5 |
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+-----------------+-------+-------+--------+
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| flreg1_limit | 0x3ff | 0x7ff | 0x1fff |
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+-----------------+-------+-------+--------+
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```
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Then create the flash descriptor:
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```console
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$ ./bincfg ifd-x200.spec ifd-x200.set ifd.bin
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```
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#### Configuring coreboot
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Now configure coreboot. You need to select correct chip size and specify paths
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to flash descriptor and gbe dump.
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```
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Mainboard --->
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ROM chip size (8192 KB (8 MB)) # According to your chip
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(0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MB chip / 0x1ffd000 for 16 MB chip
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Chipset --->
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[*] Add Intel descriptor.bin file
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# Note: if you used bincfg, specify path to generated util/bincfg/ifd.bin
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(/path/to/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file
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[*] Add gigabit ethernet configuration
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(/path/to/flashregion_3_gbe.bin) Path to gigabit ethernet configuration
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```
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Then build coreboot and flash whole `build/coreboot.rom` to the chip.
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## Installing with ME firmware
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To install coreboot and keep ME working, you don't need to do anything special
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with the flash descriptor. Just flash only `bios` externally and don't touch any
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other regions:
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```console
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# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios
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```
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## Flash layout
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The flash layouts of the OEM firmware are as follows:
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```eval_rst
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+---------------------------------+---------------------------------+
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| 4 MB chip | 8 MB chip |
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+=================================+=================================+
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| .. code-block:: none | .. code-block:: none |
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| | |
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| 00000000:00000fff fd | 00000000:00000fff fd |
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| 00001000:001f5fff me | 00001000:005f5fff me |
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| 001f6000:001f7fff gbe | 005f6000:005f7fff gbe |
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| 001f8000:001fffff pd | 005f8000:005fffff pd |
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| 00200000:003fffff bios | 00600000:007fffff bios |
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| 00290000:002affff ec | 00690000:006affff ec |
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| 003e0000:003fffff bootblock | 007e0000:007fffff bootblock |
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+---------------------------------+---------------------------------+
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```
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On each boot of vendor BIOS `ec` area in flash is checked for having firmware
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there, and if there is one, it proceedes to update firmware on H8S/2116 (when
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both external power and main battery are attached). Once update is performed,
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first 64 KB of `ec` area is erased. Visit
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[thinkpad-ec repository](https://github.com/hamishcoleman/thinkpad-ec) to learn
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more about how to extract EC firmware from vendor updates.
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