From ef8654554f07f4c51130781dee3becbad1d2c618 Mon Sep 17 00:00:00 2001 From: zhixingma Date: Tue, 21 Sep 2021 10:39:52 -0700 Subject: [PATCH] mb/intel/adlrvp_m: Enable HECI1 communication The patch enables HECI1 interface to allow OS applications to communicate with CSE. TEST=Verify PCI device 0:16.0 exposed in the lspci output Signed-off-by: zhixingma Change-Id: Ifd338345caa183f03097f1003080992da70296ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/57813 Tested-by: build bot (Jenkins) Reviewed-by: Sridhar Siricilla Reviewed-by: Rizwan Qureshi --- src/mainboard/intel/adlrvp/devicetree_m.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 2c50c289e5..5d24a420c7 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -27,6 +27,9 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" + # Enable HECI1 communication + register "HeciEnabled" = "1" + # FSP configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0 register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1