mb/protectli/vault_cml: Add Comet Lake 6 port board support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If1b4f9c8245a082ff875ae9c6102a1c45e677d0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This commit is contained in:
Michał Żygowski
Felix Held
parent
71b4e29566
commit
ef886c4ede
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@ -168,6 +168,7 @@ The boards in this section are not real mainboards, but emulators.
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- [FW2B / FW4B](protectli/fw2b_fw4b.md)
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- [FW6A / FW6B / FW6C](protectli/fw6.md)
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- [VP4630 / VP4650 / VP4670](protectli/vp46xx.md)
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## Roda
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@ -0,0 +1,135 @@
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# Protectli Vault VP46xx series
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This page describes how to run coreboot on the [Protectli VP46xx].
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## Required proprietary blobs
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To build a minimal working coreboot image some blobs are required (assuming
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only the BIOS region is being modified).
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```eval_rst
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+-----------------+---------------------------------+---------------------+
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| Binary file | Apply | Required / Optional |
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+=================+=================================+=====================+
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| FSP-M, FSP-S | Intel Firmware Support Package | Required |
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+-----------------+---------------------------------+---------------------+
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| microcode | CPU microcode | Required |
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+-----------------+---------------------------------+---------------------+
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```
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FSP-M and FSP-S are obtained after splitting the Comet Lake FSP binary (done
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automatically by the coreboot build system and included into the image) from
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the `3rdparty/fsp` submodule. VP4630 and VP4650 use CometLake2 FSP and VP4670
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use CometLake1 FSP (see [variants](#variants) section), so be sure to select
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the correct board in the coreboot's menuconfig, otherwise the platform will not
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succeed on memory initialization.
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Microcode updates are automatically included into the coreboot image by build
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system from the `3rdparty/intel-microcode` submodule.
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## Flashing coreboot
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### Internal programming
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The main SPI flash can be accessed using [flashrom]. The first version
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supporting the chipset is flashrom v1.2. Firmware an be easily flashed
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with internal programmer (either BIOS region or full image).
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### External programming
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The system has an internal flash chip which is a 16 MiB socketed SOIC-8 chip.
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This chip is located on the top side of the case (the lid side). One has to
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remove 4 top cover screws and lift up the lid. The flash chip is near the M.2
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WiFi slot connector. Remove the chip from socket and use a clip to program the
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chip. Specifically, it's a KH25L12835F (3.3V) which is a clone of Macronix
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MX25L12835F - [datasheet][MX25L12835F].
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## Known issues
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- After flashing with external programmer it is always required to reset RTC
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with a jumper or disconnect the coin cell temporarily. Only then the platform
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will boot after flashing.
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## Working
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- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux)
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- 6 Ethernet ports
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- HDMI, DisplayPort and USB-C Display Port with libgfxinit and FSP GOP
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- flashrom
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- M.2 WiFi
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- M.2 4G LTE
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- M.2 SATA and NVMe
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- 2.5'' SATA SSD
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- eMMC
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- Super I/O serial port 0 via front microUSB connector (Fintek F81232 USB to
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UART adapter present on board)
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- SMBus (reading SPD from DIMMs)
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- Initialization with CometLake FSP 2.0
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- SeaBIOS payload (version rel-1.16.0)
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- TianoCore UEFIPayload
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- LPC TPM module (using Protectli custom-designed module with Infineon SLB9660)
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- Reset switch
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- Booting Debian, Ubuntu, FreeBSD
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## Variants
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There are 3 variants of VP46xx boards: VP4630, VP4650 and VP4670. They differ
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only in used SoC and some units may come with different Super I/O chips, either
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ITE IT8786E or IT8784E, but the configuration is the same on this platform.
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- VP4630:
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | Intel Core i3-10110U |
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+------------------+--------------------------------------------------+
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| PCH | Intel Comet Lake U Premium |
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+------------------+--------------------------------------------------+
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| Super I/O, EC | ITE IT8786E/IT8784E |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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- VP4650:
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | Intel Core i5-10210U |
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+------------------+--------------------------------------------------+
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| PCH | Intel Comet Lake U Premium |
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+------------------+--------------------------------------------------+
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| Super I/O, EC | ITE IT8786E/IT8784E |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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- VP4670:
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | Intel Core i7-10810U |
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+------------------+--------------------------------------------------+
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| PCH | Intel Comet Lake U Premium |
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+------------------+--------------------------------------------------+
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| Super I/O, EC | ITE IT8786E/IT8784E |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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## Useful links
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- [VP4600 Hardware Overview](https://protectli.com/kb/vp4600-hardware-overview/)
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- [VP4630 Product Page](https://protectli.com/product/vp4630/)
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- [Protectli TPM module](https://protectli.com/product/tpm-module/)
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[Protectli VP46xx]: https://protectli.com/vault-6-port/
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[MX25L12835F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf
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[flashrom]: https://flashrom.org/Flashrom
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Binary file not shown.
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After Width: | Height: | Size: 37 KiB |
Binary file not shown.
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After Width: | Height: | Size: 48 KiB |
Binary file not shown.
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After Width: | Height: | Size: 35 KiB |
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@ -0,0 +1,13 @@
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CONFIG_VENDOR_PROTECTLI=y
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CONFIG_BOARD_PROTECTLI_VP4630_VP4650=y
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CONFIG_TPM_MEASURED_BOOT=y
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CONFIG_SMMSTORE_SIZE=0x40000
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CONFIG_TPM2=y
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CONFIG_POST_IO_PORT=0x80
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CONFIG_PAYLOAD_EDK2=y
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CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
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CONFIG_EDK2_BOOT_TIMEOUT=6
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CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
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# CONFIG_EDK2_FULL_SCREEN_SETUP is not set
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CONFIG_EDK2_SD_MMC_TIMEOUT=10
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CONFIG_EDK2_SERIAL_SUPPORT=y
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@ -0,0 +1,13 @@
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CONFIG_VENDOR_PROTECTLI=y
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CONFIG_BOARD_PROTECTLI_VP4670=y
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CONFIG_TPM_MEASURED_BOOT=y
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CONFIG_SMMSTORE_SIZE=0x40000
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CONFIG_TPM2=y
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CONFIG_POST_IO_PORT=0x80
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CONFIG_PAYLOAD_EDK2=y
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CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
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CONFIG_EDK2_BOOT_TIMEOUT=6
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CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
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# CONFIG_EDK2_FULL_SCREEN_SETUP is not set
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CONFIG_EDK2_SD_MMC_TIMEOUT=10
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CONFIG_EDK2_SERIAL_SUPPORT=y
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@ -0,0 +1,67 @@
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if BOARD_PROTECTLI_VP4630_VP4650 || BOARD_PROTECTLI_VP4670
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select GFX_GMA_IGNORE_PRESENCE_STRAPS
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_INTEL_PTT
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select MAINBOARD_HAS_LIBGFXINIT
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select MEMORY_MAPPED_TPM
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select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
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select SOC_INTEL_COMETLAKE_1 if BOARD_PROTECTLI_VP4670
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select SOC_INTEL_COMETLAKE_2 if BOARD_PROTECTLI_VP4630_VP4650
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SPI_FLASH_MACRONIX
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select SUPERIO_ITE_IT8786E
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config MAINBOARD_DIR
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default "protectli/vault_cml"
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config MAINBOARD_PART_NUMBER
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default "VP4630/VP4650" if BOARD_PROTECTLI_VP4630_VP4650
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default "VP4670" if BOARD_PROTECTLI_VP4670
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config MAINBOARD_FAMILY
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default "Vault Pro"
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config DIMM_MAX
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default 2
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config DIMM_SPD_SIZE
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default 512
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config CBFS_SIZE
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default 0xa00000
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config GFX_GMA_PANEL_1_ON_EDP
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default n
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config VBOOT
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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select GBB_FLAG_DISABLE_FWMP
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select GBB_FLAG_DISABLE_LID_SHUTDOWN
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select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
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select VBOOT_ALWAYS_ENABLE_DISPLAY
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select VBOOT_NO_BOARD_SUPPORT
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config VBOOT_SLOTS_RW_A
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default y if VBOOT
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
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config BEEP_ON_BOOT
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bool "Beep on successful boot"
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default y
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help
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Make the platform beep using the PC speaker in final coreboot phase.
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May serve as a useful indicator in headless mode that platform is
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properly booting.
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endif
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@ -0,0 +1,5 @@
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config BOARD_PROTECTLI_VP4630_VP4650
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bool "VP4630/VP4650"
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config BOARD_PROTECTLI_VP4670
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bool "VP4670"
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += bootblock.c
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bootblock-y += gpio.c
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romstage-y += romstage.c
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ramstage-y += mainboard.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
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ramstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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all-y += die.c
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smm-y += die.c
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@ -0,0 +1 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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@ -0,0 +1 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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FLASH@0xff000000 0x1000000 {
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SI_ALL 6M {
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SI_DESC 4K
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SI_ME
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}
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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RECOVERY_MRC_CACHE 64K
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RW_MRC_CACHE 64K
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}
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SMMSTORE(PRESERVE) 256K
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FMAP 0x800
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COREBOOT(CBFS)
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}
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@ -0,0 +1,6 @@
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Vendor name: Protectli
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Board name: VP4630/VP4650/VP4670
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Category: sbc
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ROM protocol: SPI
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ROM socketed: y
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Flashrom support: y
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include <superio/ite/common/ite.h>
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#include <superio/ite/it8786e/it8786e.h>
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#include "gpio.h"
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#define UART_DEV PNP_DEV(0x2e, IT8786E_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, IT8786E_GPIO)
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void bootblock_mainboard_early_init(void)
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{
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/* CLKIN freq 24MHz, Ext CLKIN for Watchdog, Internal VCC_OK */
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ite_reg_write(GPIO_DEV, 0x23, 0x49);
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/* Set pin native functions */
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ite_reg_write(GPIO_DEV, 0x26, 0x00);
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/* Set GPIOS exposed on pin header as GPIO functions */
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ite_reg_write(GPIO_DEV, 0x29, 0xc0);
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/* External CLKIN PCICLK */
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ite_reg_write(GPIO_DEV, 0x71, 0x08);
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/* Enable 3VSB during Suspend-to-RAM */
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ite_enable_3vsbsw(GPIO_DEV);
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/* Delay PWROK2 after 3VSBSW# during resume from Suspend-to-RAM */
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ite_delay_pwrgd3(GPIO_DEV);
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ite_kill_watchdog(GPIO_DEV);
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ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
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}
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void bootblock_mainboard_init(void)
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{
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const struct pad_config *pads;
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size_t num;
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pads = board_gpio_table(&num);
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gpio_configure_pads(pads, num);
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}
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@ -0,0 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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me_state=Enable
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@ -0,0 +1,40 @@
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# SPDX-License-Identifier: GPL-2.0-only
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entries
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0 384 r 0 reserved_memory
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 2 boot_option
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388 4 h 0 reboot_counter
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395 3 e 3 debug_level
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398 1 e 4 me_state
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400 4 h 0 me_state_counter
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984 16 h 0 check_sum
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enumerations
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1 0 Disable
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1 1 Enable
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2 0 Fallback
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2 1 Normal
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3 0 Emergency
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3 1 Alert
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3 2 Critical
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3 3 Error
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3 4 Warning
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3 5 Notice
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3 6 Info
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3 7 Debug
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3 8 Spew
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4 0 Enable
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4 1 Disable
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checksums
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checksum 392 983 984
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Binary file not shown.
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@ -0,0 +1,248 @@
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chip soc/intel/cannonlake
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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register "cpu_pl2_4_cfg" = "baseline"
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register "gen1_dec" = "0x00fc0201"
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register "gen2_dec" = "0x007c0a01"
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register "gen3_dec" = "0x000c03e1"
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register "gen4_dec" = "0x001c02e1"
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# GPIO
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register "PchUnlockGpioPads" = "1"
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register "gpe0_dw0" = "0x2"
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register "gpe0_dw1" = "0x3"
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register "gpe0_dw2" = "0xd"
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# FSP configuration
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register "SaGv" = "SaGv_Enabled"
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register "ScsEmmcHs400Enabled" = "1"
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# Enable eDP device
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register "DdiPortEdp" = "1" # Display Port
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# Enable HPD for DDI ports B/C
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register "DdiPortBHpd" = "1" # HDMI
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register "DdiPortCHpd" = "1" # USB Type-C
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# Enable DDC for DDI port B
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register "DdiPortBDdc" = "1" # HDMI
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register "PchHdaAudioLinkHda" = "1"
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# Misc
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register "AcousticNoiseMitigation" = "1"
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# Power
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register "PchPmSlpS3MinAssert" = "3" # 50ms
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register "PchPmSlpS4MinAssert" = "1" # 1s
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register "PchPmSlpSusMinAssert" = "2" # 500ms
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register "PchPmSlpAMinAssert" = "4" # 2s
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register "tcc_offset" = "20" # TCC of 80C
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# Enable SERIRQ continuous
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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register "SkipExtGfxScan" = "1"
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register "enable_c6dram" = "1"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[2]" = "1"
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register "PcieRpEnable[4]" = "1" # LAN1
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register "PcieRpEnable[5]" = "1" # LAN2
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register "PcieRpEnable[6]" = "1" # LAN3
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register "PcieRpEnable[7]" = "1" # LAN4
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register "PcieRpEnable[8]" = "1" # LAN5
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register "PcieRpEnable[9]" = "1" # LAN6
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register "PcieRpEnable[11]" = "1" # M.2 WiFi
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register "PcieRpEnable[12]" = "1" # M.2 NVMe x4
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# Enable Advanced Error Reporting for RP 5-10, 12, 13
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register "PcieRpAdvancedErrorReporting[4]" = "1"
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register "PcieRpAdvancedErrorReporting[5]" = "1"
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register "PcieRpAdvancedErrorReporting[6]" = "1"
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register "PcieRpAdvancedErrorReporting[7]" = "1"
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register "PcieRpAdvancedErrorReporting[8]" = "1"
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register "PcieRpAdvancedErrorReporting[9]" = "1"
|
||||
register "PcieRpAdvancedErrorReporting[11]" = "1"
|
||||
register "PcieRpAdvancedErrorReporting[12]" = "1"
|
||||
|
||||
# Enable Latency Tolerance Reporting Mechanism RP 5-10, 12, 13
|
||||
register "PcieRpLtrEnable[4]" = "1"
|
||||
register "PcieRpLtrEnable[5]" = "1"
|
||||
register "PcieRpLtrEnable[6]" = "1"
|
||||
register "PcieRpLtrEnable[7]" = "1"
|
||||
register "PcieRpLtrEnable[8]" = "1"
|
||||
register "PcieRpLtrEnable[9]" = "1"
|
||||
register "PcieRpLtrEnable[11]" = "1"
|
||||
register "PcieRpLtrEnable[12]" = "1"
|
||||
|
||||
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
|
||||
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
|
||||
register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
|
||||
register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE"
|
||||
register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
|
||||
register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"
|
||||
|
||||
# USB related
|
||||
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
|
||||
USB_PORT_WAKE_ENABLE(2) | \
|
||||
USB_PORT_WAKE_ENABLE(3) | \
|
||||
USB_PORT_WAKE_ENABLE(4) | \
|
||||
USB_PORT_WAKE_ENABLE(5) | \
|
||||
USB_PORT_WAKE_ENABLE(6) | \
|
||||
USB_PORT_WAKE_ENABLE(7) | \
|
||||
USB_PORT_WAKE_ENABLE(8) | \
|
||||
USB_PORT_WAKE_ENABLE(9)"
|
||||
|
||||
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
|
||||
USB_PORT_WAKE_ENABLE(2) | \
|
||||
USB_PORT_WAKE_ENABLE(3) | \
|
||||
USB_PORT_WAKE_ENABLE(4)"
|
||||
|
||||
register "PchUsb2PhySusPgDisable" = "1"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M2 WiFi
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # 4G/LTE
|
||||
register "usb2_ports[9]" = "USB2_PORT_EMPTY"
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
register "usb3_ports[4]" = "USB3_PORT_EMPTY"
|
||||
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
|
||||
|
||||
register "SerialIoDevMode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
device cpu_cluster 0 on end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 on end # SA Thermal device
|
||||
device pci 08.0 off end # Gaussian Mixture Model
|
||||
device pci 12.0 on end # Thermal Subsystem
|
||||
device pci 12.5 off end # UFS SCS
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.5 off end # SDCard
|
||||
device pci 15.0 off end # I2C #0
|
||||
device pci 15.1 off end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 off end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 19.0 off end # I2C #4
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 off end # UART #2
|
||||
device pci 1a.0 on end # eMMC
|
||||
device pci 1c.0 off end # PCI Express Port 1
|
||||
device pci 1c.1 off end # PCI Express Port 2
|
||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1c.4 on end # PCI Express Port 5 LAN1
|
||||
device pci 1c.5 on end # PCI Express Port 6 LAN2
|
||||
device pci 1c.6 on end # PCI Express Port 7 LAN3
|
||||
device pci 1c.7 on end # PCI Express Port 8 LAN4
|
||||
device pci 1d.0 on end # PCI Express Port 9 LAN5
|
||||
device pci 1d.1 on end # PCI Express Port 10 LAN6
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 on end # PCI Express Port 12 M.2 WiFi
|
||||
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
|
||||
"M.2/E 2230 (M2_WIFI2)" "SlotDataBusWidth1X"
|
||||
device pci 1d.4 on # PCI Express Port 13 NVMe
|
||||
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
|
||||
"M.2/M 2280 (J1)" "SlotDataBusWidth4X"
|
||||
end
|
||||
device pci 1d.5 off end # PCI Express Port 14
|
||||
device pci 1d.6 off end # PCI Express Port 15
|
||||
device pci 1d.7 off end # PCI Express Port 16
|
||||
device pci 1e.0 off end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on
|
||||
chip superio/ite/it8786e
|
||||
register "TMPIN1.mode" = "THERMAL_PECI"
|
||||
register "TMPIN1.offset" = "0x63"
|
||||
register "TMPIN2.mode" = "THERMAL_MODE_DISABLED"
|
||||
register "TMPIN3.mode" = "THERMAL_MODE_DISABLED"
|
||||
register "ec.vin_mask" = "VIN_ALL"
|
||||
register "ec.smbus_24mhz" = "1"
|
||||
register "ec.smbus_en" = "1"
|
||||
# FAN1 is CPU fan (connector on board)
|
||||
register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
|
||||
register "FAN1.smart.tmpin" = " 1"
|
||||
register "FAN1.smart.tmp_off" = "40"
|
||||
register "FAN1.smart.tmp_start" = "60"
|
||||
register "FAN1.smart.tmp_full" = "85"
|
||||
register "FAN1.smart.tmp_delta" = " 2"
|
||||
register "FAN1.smart.pwm_start" = "20"
|
||||
register "FAN1.smart.slope" = "24"
|
||||
register "FAN2.mode" = "FAN_MODE_OFF"
|
||||
register "FAN3.mode" = "FAN_MODE_OFF"
|
||||
device pnp 2e.1 on # COM 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 on # COM 2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 off end # Printer Port
|
||||
device pnp 2e.4 on # Environment Controller
|
||||
io 0x60 = 0xa40
|
||||
io 0x62 = 0xa30
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.5 off end # Keyboard
|
||||
device pnp 2e.6 off end # Mouse
|
||||
device pnp 2e.7 off end # GPIO
|
||||
device pnp 2e.8 off end # COM 3
|
||||
device pnp 2e.9 off end # COM 4
|
||||
device pnp 2e.a off end # CIR
|
||||
device pnp 2e.b off end # COM 5
|
||||
device pnp 2e.c off end # COM 6
|
||||
end
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 hidden end # P2SB
|
||||
device pci 1f.2 hidden end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <pc80/i8254.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <delay.h>
|
||||
#include <gpio.h>
|
||||
|
||||
static void beep_and_blink(void)
|
||||
{
|
||||
static uint8_t blink = 0;
|
||||
static uint8_t beep_count = 0;
|
||||
|
||||
gpio_set(GPP_E8, blink);
|
||||
/* Beep 12 times at most, constant beeps may be annoying */
|
||||
if (beep_count < 12) {
|
||||
beep(800, 300);
|
||||
mdelay(200);
|
||||
beep_count++;
|
||||
} else {
|
||||
mdelay(500);
|
||||
}
|
||||
|
||||
blink ^= 1;
|
||||
}
|
||||
|
||||
void die_notify(void)
|
||||
{
|
||||
if (ENV_POSTCAR)
|
||||
return;
|
||||
|
||||
/* Make SATA LED blink and use PC SPKR */
|
||||
gpio_output(GPP_E8, 0);
|
||||
|
||||
while (1) {
|
||||
beep_and_blink();
|
||||
beep_and_blink();
|
||||
beep_and_blink();
|
||||
beep_and_blink();
|
||||
delay(2);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725
|
||||
)
|
||||
{
|
||||
#include <acpi/dsdt_top.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/platform.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Device (\_SB.PCI0)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
||||
#include <soc/intel/cannonlake/acpi/southbridge.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(eDP,
|
||||
DP2,
|
||||
HDMI1,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,442 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef CFG_GPIO_H
|
||||
#define CFG_GPIO_H
|
||||
|
||||
#include "gpio.h"
|
||||
|
||||
/* Pad configuration was generated automatically using intelp2m utility */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
|
||||
/* ------- GPIO Community 0 ------- */
|
||||
/* ------- GPIO Group GPP_A ------- */
|
||||
|
||||
/* GPP_A0 - RCIN# */
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
/* GPP_A1 - LAD0 */
|
||||
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
|
||||
/* GPP_A2 - LAD1 */
|
||||
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
|
||||
/* GPP_A3 - LAD2 */
|
||||
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
|
||||
/* GPP_A4 - LAD3 */
|
||||
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
|
||||
/* GPP_A5 - LFRAME# */
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
/* GPP_A6 - SERIRQ */
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
/* GPP_A7 - PIRQA# */
|
||||
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
|
||||
/* GPP_A8 - CLKRUN# */
|
||||
PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1),
|
||||
/* GPP_A9 - CLKOUT_LPC0 */
|
||||
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
|
||||
/* GPP_A10 - CLKOUT_LPC1 */
|
||||
PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
|
||||
/* GPP_A11 - PME# */
|
||||
PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),
|
||||
/* GPP_A12 - GPIO */
|
||||
PAD_NC(GPP_A12, NONE),
|
||||
/* GPP_A13 - GPIO */
|
||||
PAD_NC(GPP_A13, NONE),
|
||||
/* GPP_A14 - GPIO */
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
/* GPP_A15 - GPIO */
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
/* GPP_A16 - GPIO */
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
/* GPP_A17 - GPIO */
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
/* GPP_A18 - GPIO */
|
||||
PAD_NC(GPP_A18, NONE),
|
||||
/* GPP_A19 - GPIO */
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
/* GPP_A20 - GPIO */
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
/* GPP_A21 - GPIO */
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
/* GPP_A22 - GPIO */
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
/* GPP_A23 - GPIO */
|
||||
PAD_NC(GPP_A23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_B ------- */
|
||||
|
||||
/* GPP_B0 - CORE_VID0 */
|
||||
PAD_NC(GPP_B0, NONE),
|
||||
/* GPP_B1 - CORE_VID1 */
|
||||
PAD_NC(GPP_B1, NONE),
|
||||
/* GPP_B2 - GPIO */
|
||||
PAD_NC(GPP_B2, NONE),
|
||||
/* GPP_B3 - GPIO */
|
||||
PAD_NC(GPP_B3, NONE),
|
||||
/* GPP_B4 - GPIO */
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
/* GPP_B5 - GPIO */
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
/* GPP_B6 - GPIO */
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
/* GPP_B7 - GPIO */
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
/* GPP_B8 - GPIO */
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
/* GPP_B9 - GPIO */
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
/* GPP_B10 - GPIO */
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
/* GPP_B11 - EXT_PWR_GATE# */
|
||||
PAD_NC(GPP_B11, NONE),
|
||||
/* GPP_B12 - SLP_S0# */
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* GPP_B13 - PLTRST# */
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* GPP_B14 - SPKR */
|
||||
PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1),
|
||||
/* GPP_B15 - GPIO */
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
/* GPP_B16 - GPIO */
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
/* GPP_B17 - GPIO */
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
/* GPP_B18 - GPIO */
|
||||
PAD_NC(GPP_B18, NONE),
|
||||
/* GPP_B19 - GPIO */
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
/* GPP_B20 - GPIO */
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
/* GPP_B21 - GPIO */
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
/* GPP_B22 - GPIO */
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
/* GPP_B23 - GPIO */
|
||||
PAD_NC(GPP_B23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_G ------- */
|
||||
|
||||
/* GPP_G0 - GPIO */
|
||||
PAD_NC(GPP_G0, NONE),
|
||||
/* GPP_G1 - GPIO */
|
||||
PAD_NC(GPP_G1, NONE),
|
||||
/* GPP_G2 - GPIO */
|
||||
PAD_NC(GPP_G2, NONE),
|
||||
/* GPP_G3 - GPIO */
|
||||
PAD_NC(GPP_G3, NONE),
|
||||
/* GPP_G4 - GPIO */
|
||||
PAD_NC(GPP_G4, NONE),
|
||||
/* GPP_G5 - SD3_CD# */
|
||||
PAD_NC(GPP_G5, NONE),
|
||||
/* GPP_G6 - GPIO */
|
||||
PAD_NC(GPP_G6, NONE),
|
||||
/* GPP_G7 - SD3_WP */
|
||||
PAD_NC(GPP_G7, NONE),
|
||||
|
||||
/* ------- GPIO Group SPI ------- */
|
||||
|
||||
/* ------- GPIO Community 1 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
|
||||
/* GPP_D0 - GPIO */
|
||||
PAD_NC(GPP_D0, NONE),
|
||||
/* GPP_D1 - GPIO */
|
||||
PAD_NC(GPP_D1, NONE),
|
||||
/* GPP_D2 - GPIO */
|
||||
PAD_NC(GPP_D2, NONE),
|
||||
/* GPP_D3 - GPIO */
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
/* GPP_D4 - GPIO */
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
/* GPP_D5 - GPIO */
|
||||
PAD_NC(GPP_D5, NONE),
|
||||
/* GPP_D6 - GPIO */
|
||||
PAD_NC(GPP_D6, NONE),
|
||||
/* GPP_D7 - GPIO */
|
||||
PAD_NC(GPP_D7, NONE),
|
||||
/* GPP_D8 - GPIO */
|
||||
PAD_NC(GPP_D8, NONE),
|
||||
/* GPP_D9 - GPIO */
|
||||
PAD_NC(GPP_D9, NONE),
|
||||
/* GPP_D10 - GPIO */
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
/* GPP_D11 - GPIO */
|
||||
PAD_NC(GPP_D11, NONE),
|
||||
/* GPP_D12 - GPIO */
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
/* GPP_D13 - GPIO */
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
/* GPP_D14 - GPIO */
|
||||
PAD_NC(GPP_D14, NONE),
|
||||
/* GPP_D15 - GPIO */
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
/* GPP_D16 - GPIO */
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
/* GPP_D17 - GPIO */
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
/* GPP_D18 - GPIO */
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
/* GPP_D19 - GPIO */
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
/* GPP_D20 - GPIO */
|
||||
PAD_NC(GPP_D20, NONE),
|
||||
/* GPP_D21 - SPI1_IO2 */
|
||||
PAD_NC(GPP_D21, NONE),
|
||||
/* GPP_D22 - SPI1_IO3 */
|
||||
PAD_NC(GPP_D22, NONE),
|
||||
/* GPP_D23 - GPIO */
|
||||
PAD_NC(GPP_D23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
|
||||
/* GPP_F0 - GPIO */
|
||||
PAD_NC(GPP_F0, NONE),
|
||||
/* GPP_F1 - GPIO */
|
||||
PAD_NC(GPP_F1, NONE),
|
||||
/* GPP_F2 - GPIO */
|
||||
PAD_NC(GPP_F2, NONE),
|
||||
/* GPP_F3 - GPIO */
|
||||
PAD_NC(GPP_F3, NONE),
|
||||
/* GPP_F4 - GPIO */
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
/* GPP_F5 - GPIO */
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
/* GPP_F6 - GPIO */
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
/* GPP_F7 - GPIO */
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
/* GPP_F8 - GPIO */
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
/* GPP_F9 - GPIO */
|
||||
PAD_NC(GPP_F9, NONE),
|
||||
/* GPP_F10 - GPIO */
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
/* GPP_F11 - EMMC_CMD */
|
||||
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
|
||||
/* GPP_F12 - EMMC_DATA0 */
|
||||
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||
/* GPP_F13 - EMMC_DATA1 */
|
||||
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
|
||||
/* GPP_F14 - EMMC_DATA2 */
|
||||
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
|
||||
/* GPP_F15 - EMMC_DATA3 */
|
||||
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
|
||||
/* GPP_F16 - EMMC_DATA4 */
|
||||
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||
/* GPP_F17 - EMMC_DATA5 */
|
||||
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
||||
/* GPP_F18 - EMMC_DATA6 */
|
||||
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
|
||||
/* GPP_F19 - EMMC_DATA7 */
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
/* GPP_F20 - EMMC_RCLK */
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
/* GPP_F21 - EMMC_CLK */
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
/* GPP_F22 - EMMC_RESET# */
|
||||
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||
/* GPP_F23 - GPIO */
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_H ------- */
|
||||
|
||||
/* GPP_H0 - GPIO */
|
||||
PAD_NC(GPP_H0, NONE),
|
||||
/* GPP_H1 - GPIO# */
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
/* GPP_H2 - GPIO */
|
||||
PAD_NC(GPP_H2, NONE),
|
||||
/* GPP_H3 - GPIO */
|
||||
PAD_NC(GPP_H3, NONE),
|
||||
/* GPP_H4 - GPIO */
|
||||
PAD_NC(GPP_H4, NONE),
|
||||
/* GPP_H5 - GPIO */
|
||||
PAD_NC(GPP_H5, NONE),
|
||||
/* GPP_H6 - GPIO */
|
||||
PAD_NC(GPP_H6, NONE),
|
||||
/* GPP_H7 - GPIO */
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
/* GPP_H8 - GPIO */
|
||||
PAD_NC(GPP_H8, NONE),
|
||||
/* GPP_H9 - GPIO */
|
||||
PAD_NC(GPP_H9, NONE),
|
||||
/* GPP_H10 - GPIO */
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
/* GPP_H11 - GPIO */
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
/* GPP_H12 - GPIO */
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
/* GPP_H13 - GPIO */
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
/* GPP_H14 - GPIO */
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
/* GPP_H15 - GPIO */
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
/* GPP_H16 - GPIO */
|
||||
PAD_NC(GPP_H16, NONE),
|
||||
/* GPP_H17 - GPIO */
|
||||
PAD_NC(GPP_H17, NONE),
|
||||
/* GPP_H18 - CPU_C10_GATE# */
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
/* GPP_H19 - GPIO */
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
/* GPP_H20 - GPIO */
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
/* GPP_H21 - GPIO */
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
/* GPP_H22 - GPIO */
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
/* GPP_H23 - GPIO */
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
|
||||
/* ------- GPIO Group VGPIO ------- */
|
||||
|
||||
/* ------- GPIO Community 2 ------- */
|
||||
|
||||
/* ------- GPIO Group GPD ------- */
|
||||
|
||||
/* GPD0 - BATLOW# */
|
||||
PAD_CFG_NF(GPD0, NONE, RSMRST, NF1),
|
||||
/* GPD1 - ACPRESENT */
|
||||
PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1),
|
||||
/* GPD2 - LAN_WAKE# */
|
||||
PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1),
|
||||
/* GPD3 - PRWBTN# */
|
||||
PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1),
|
||||
/* GPD4 - SLP_S3# */
|
||||
PAD_CFG_NF(GPD4, NONE, RSMRST, NF1),
|
||||
/* GPD5 - SLP_S4# */
|
||||
PAD_CFG_NF(GPD5, NONE, RSMRST, NF1),
|
||||
/* GPD6 - SLP_A# */
|
||||
PAD_NC(GPD6, NONE),
|
||||
/* GPD7 - GPIO */
|
||||
PAD_NC(GPD7, NONE),
|
||||
/* GPD8 - SUSCLK */
|
||||
PAD_NC(GPD8, NONE),
|
||||
/* GPD9 - GPIO */
|
||||
PAD_NC(GPD9, NONE),
|
||||
/* GPD10 - SLP_S5# */
|
||||
PAD_NC(GPD10, NONE),
|
||||
/* GPD11 - GPIO */
|
||||
PAD_NC(GPD11, NONE),
|
||||
|
||||
/* ------- GPIO Community 3 ------- */
|
||||
|
||||
/* ------- GPIO Group AZA ------- */
|
||||
|
||||
/* ------- GPIO Group CPU ------- */
|
||||
|
||||
/* ------- GPIO Community 4 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_C ------- */
|
||||
|
||||
/* GPP_C0 - SMBCLK */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
/* GPP_C1 - SMBDATA */
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
/* GPP_C2 - GPIO */
|
||||
PAD_NC(GPP_C2, NONE),
|
||||
/* GPP_C3 - SML0CLK */
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
/* GPP_C4 - SML0DATA */
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
/* GPP_C5 - GPIO */
|
||||
PAD_NC(GPP_C5, NONE),
|
||||
/* GPP_C6 - SML1CLK */
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
/* GPP_C7 - SML1DATA */
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
/* GPP_C8 - GPIO */
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
/* GPP_C9 - GPIO */
|
||||
PAD_NC(GPP_C9, NONE),
|
||||
/* GPP_C10 - GPIO */
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
/* GPP_C11 - GPIO */
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
/* GPP_C12 - GPIO */
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
/* GPP_C13 - GPIO */
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
/* GPP_C14 - GPIO */
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
/* GPP_C15 - GPIO */
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
/* GPP_C16 - GPIO */
|
||||
PAD_NC(GPP_C16, NONE),
|
||||
/* GPP_C17 - GPIO */
|
||||
PAD_NC(GPP_C17, NONE),
|
||||
/* GPP_C18 - GPIO */
|
||||
PAD_NC(GPP_C18, NONE),
|
||||
/* GPP_C19 - GPIO */
|
||||
PAD_NC(GPP_C19, NONE),
|
||||
/* GPP_C20 - GPIO */
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
/* GPP_C21 - GPIO */
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
/* GPP_C22 - GPIO */
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
/* GPP_C23 - GPIO */
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
|
||||
/* GPP_E0 - GPIO */
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
/* GPP_E1 - GPIO */
|
||||
PAD_NC(GPP_E1, NONE),
|
||||
/* GPP_E2 - SATAXPCIE2 */
|
||||
PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1),
|
||||
/* GPP_E3 - GPIO */
|
||||
PAD_NC(GPP_E3, NONE),
|
||||
/* GPP_E4 - GPIO */
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
/* GPP_E5 - GPIO */
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
/* GPP_E6 - GPIO */
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
/* GPP_E7 - GPIO */
|
||||
PAD_NC(GPP_E7, NONE),
|
||||
/* GPP_E8 - SATALED# */
|
||||
PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1),
|
||||
/* GPP_E9 - RESERVED */
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
/* GPP_E10 - RESERVED */
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
/* GPP_E11 - GPIO */
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
/* GPP_E12 - GPIO */
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
/* GPP_E13 - DDPB_HPD0 */
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
/* GPP_E14 - DDPC_HPD1 */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
/* GPP_E15 - DDPD_HPD2 */
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
/* GPP_E16 - GPIO */
|
||||
PAD_NC(GPP_E16, NONE),
|
||||
/* GPP_E17 - EDP_HPD */
|
||||
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
/* GPP_E18 - DPPB_CTRLCLK */
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
/* GPP_E19 - DPPB_CTRLDATA */
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
|
||||
/* GPP_E20 - DPPC_CTRLCLK */
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
/* GPP_E21 - DPPC_CTRLDATA */
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
/* GPP_E22 - DPPD_CTRLCLK */
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
/* GPP_E23 - DPPD_CTRLDATA */
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
|
||||
/* ------- GPIO Group JTAG ------- */
|
||||
|
||||
/* ------- GPIO Group HVMOS ------- */
|
||||
};
|
||||
|
||||
const struct pad_config *board_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
#endif /* CFG_GPIO_H */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __BASEBOARD_GPIO_H__
|
||||
#define __BASEBOARD_GPIO_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
const struct pad_config *board_gpio_table(size_t *num);
|
||||
|
||||
#endif /* __BASEBOARD_GPIO_H__ */
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0897, /* Codec Vendor / Device ID: Realtek */
|
||||
0x10ec0000, /* Subsystem ID */
|
||||
15, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(0, 0x10ec0662),
|
||||
AZALIA_PIN_CFG(0, 0x11, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x04214110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a19120),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40231105),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
|
||||
|
||||
0x8086280b, /* Codec Vendor / Device ID: Intel */
|
||||
0x80860101, /* Subsystem ID */
|
||||
2, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x03, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
};
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <cpu/x86/name.h>
|
||||
#include <device/device.h>
|
||||
#include <pc80/i8254.h>
|
||||
#include <smbios.h>
|
||||
#include <string.h>
|
||||
|
||||
const char *smbios_mainboard_product_name(void)
|
||||
{
|
||||
char processor_name[49];
|
||||
|
||||
fill_processor_name(processor_name);
|
||||
|
||||
if (strstr(processor_name, "i3-10110U") != NULL)
|
||||
return "VP4630";
|
||||
else if (strstr(processor_name, "i5-10210U") != NULL)
|
||||
return "VP4650";
|
||||
else if (strstr(processor_name, "i7-10810U") != NULL)
|
||||
return "VP4670";
|
||||
else
|
||||
return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME;
|
||||
}
|
||||
|
||||
static void mainboard_final(void *unused)
|
||||
{
|
||||
if (CONFIG(BEEP_ON_BOOT))
|
||||
beep(1500, 100);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.final = mainboard_final,
|
||||
};
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/cnl_memcfg_init.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct cnl_mb_cfg board_memcfg_cfg = {
|
||||
/* Access memory info through SMBUS. */
|
||||
.spd[0] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xA0}
|
||||
},
|
||||
.spd[1] = {
|
||||
.read_type = NOT_EXISTING,
|
||||
},
|
||||
.spd[2] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xA4}
|
||||
},
|
||||
.spd[3] = {
|
||||
.read_type = NOT_EXISTING,
|
||||
},
|
||||
|
||||
/* Baseboard uses 121, 81 and 100 rcomp resistors */
|
||||
.rcomp_resistor = {121, 81, 100},
|
||||
|
||||
/*
|
||||
* Baseboard Rcomp target values.
|
||||
*/
|
||||
.rcomp_targets = {100, 40, 20, 20, 26},
|
||||
|
||||
/* Baseboard is an interleaved design */
|
||||
.dq_pins_interleaved = 1,
|
||||
|
||||
/* Baseboard is using config 2 for vref_ca */
|
||||
.vref_ca_config = 2,
|
||||
|
||||
/* Enable Early Command Training */
|
||||
.ect = 1,
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
cannonlake_memcfg_init(&memupd->FspmConfig, &board_memcfg_cfg);
|
||||
}
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
FLASH@0xff000000 0x1000000 {
|
||||
SI_ALL 6M {
|
||||
SI_DESC 4K
|
||||
SI_ME
|
||||
}
|
||||
|
||||
RW_MISC 424K {
|
||||
UNIFIED_MRC_CACHE(PRESERVE) 128K {
|
||||
RECOVERY_MRC_CACHE 64K
|
||||
RW_MRC_CACHE 64K
|
||||
}
|
||||
SMMSTORE(PRESERVE) 256K
|
||||
RW_SHARED 0x4000 {
|
||||
SHARED_DATA@0x0 0x2000
|
||||
VBLOCK_DEV@0x2000 0x2000
|
||||
}
|
||||
RW_NVRAM(PRESERVE) 24K
|
||||
}
|
||||
|
||||
CONSOLE 0x20000
|
||||
|
||||
RW_SECTION_A {
|
||||
VBLOCK_A 0x2000
|
||||
FW_MAIN_A(CBFS)
|
||||
RW_FWID_A 0x40
|
||||
}
|
||||
|
||||
# T/B = 0
|
||||
# BP3 = 0 BP2 = 1 BP1 = 1 BP0 = 1
|
||||
WP_RO@0xC00000 0x400000 {
|
||||
RO_VPD(PRESERVE)@0x0 0x4000
|
||||
RO_SECTION@0x4000 0x3fc000 {
|
||||
FMAP@0x0 0x800
|
||||
RO_FRID@0x800 0x40
|
||||
RO_FRID_PAD@0x840 0x7c0
|
||||
GBB@0x1000 0x3000
|
||||
COREBOOT(CBFS)@0x4000 0x3f8000
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue