soc/intel/apollolake: Add PM methods to power gate PCIe
This implements GNVS variable to store the address of PERST_0, _ON/_OFF methods to power gate PCIe during S0ix entry, and PERST_0 assertion/de-assertion methods. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16351 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Vaibhav Shankar
Aaron Durbin
parent
9e81540b85
commit
ef8deaffcb
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@ -29,6 +29,7 @@
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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#include <string.h>
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#include <soc/gpio.h>
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#include "chip.h"
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#define CSTATE_RES(address_space, width, offset, address) \
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@ -175,6 +176,10 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs)
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/* Enable DPTF based on mainboard configuration */
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gnvs->dpte = cfg->dptf_enable;
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/* Assign address of PERST_0 if GPIO is defined in devicetree */
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if (cfg->prt0_gpio != GPIO_PRT0_UDEF)
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gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio);
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}
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/* Save wake source information for calculating ACPI _SWS values */
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@ -38,6 +38,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
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NHLA, 64, // 0x19 - 0x20 - NHLT Address
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NHLL, 32, // 0x21 - 0x24 - NHLT Length
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PRT0, 32, // 0x25 - 0x28 - PERST_0 Address
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/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
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Offset (0x100),
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@ -15,6 +15,7 @@
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* GNU General Public License for more details.
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*/
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#include <soc/gpio_defs.h>
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#include "gpiolib.asl"
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scope (\_SB) {
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@ -141,6 +142,38 @@ scope (\_SB) {
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Return(0xf)
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}
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}
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Scope(\_SB.PCI0) {
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/* PERST Assertion
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* Note: PERST is Active High
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*/
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Method (PRAS, 0x1, Serialized)
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{
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/*
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* Assert PERST
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* local1 - to toggle Tx pin of Dw0
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* local2 - Address of PERST
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*/
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Store (Arg0, Local2)
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Store (\_SB.GPC0 (Local2), Local1)
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Or (Local1, PAD_CFG0_TX_STATE, Local1)
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\_SB.SPC0 (Local2, Local1)
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}
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/* PERST DE-Assertion */
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Method (PRDA, 0x1, Serialized)
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{
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/*
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* De-assert PERST
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* local1 - to toggle Tx pin of Dw0
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* local2 - Address of PERST
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*/
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Store (Arg0, Local2)
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Store (\_SB.GPC0 (Local2), Local1)
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And (Local1, Not (PAD_CFG0_TX_STATE), Local1)
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\_SB.SPC0 (Local2, Local1)
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}
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}
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}
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Scope(\_GPE)
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@ -0,0 +1,67 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Scope (\_SB)
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{
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/* Get Pad Configuration DW0 register value */
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Method (GPC0, 0x1, Serialized)
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{
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/* Arg0 - GPIO DW0 address */
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Store (Arg0, Local0)
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OperationRegion (PDW0, SystemMemory, Local0, 4)
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Field (PDW0, AnyAcc, NoLock, Preserve) {
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TEMP, 32
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}
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Return (TEMP)
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}
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/* Set Pad Configuration DW0 register value */
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Method (SPC0, 0x2, Serialized)
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{
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/* Arg0 - GPIO DW0 address */
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/* Arg1 - Value for DW0 register */
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Store (Arg0, Local0)
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OperationRegion (PDW0, SystemMemory, Local0, 4)
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Field (PDW0, AnyAcc, NoLock, Preserve) {
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TEMP,32
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}
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Store (Arg1, TEMP)
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}
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/* Get Pad Configuration DW1 register value */
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Method (GPC1, 0x1, Serialized)
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{
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/* Arg0 - GPIO DW0 address */
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Store (Add (Arg0, 0x4), Local0)
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OperationRegion (PDW1, SystemMemory, Local0, 4)
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Field (PDW1, AnyAcc, NoLock, Preserve) {
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TEMP, 32
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}
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Return (TEMP)
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}
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/* Set Pad Configuration DW1 register value */
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Method (SPC1, 0x2, Serialized)
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{
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/* Arg0 - GPIO DW0 address */
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/* Arg1 - Value for DW1 register */
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Store (Add (Arg0, 0x4), Local0)
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OperationRegion (PDW1, SystemMemory, Local0, 4)
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Field(PDW1, AnyAcc, NoLock, Preserve) {
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TEMP,32
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}
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Store (Arg1, TEMP)
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}
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}
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@ -0,0 +1,126 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Device (RP01)
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{
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Name (_ADR, 0x00140000)
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Name (_DDN, "PCIe-B 0")
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Name (PDST, 0) /* present Detect status */
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/* lowest D-state supported by
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* PCIe root port during S0 state
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*/
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Name (_S0W, 4)
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/* Dynamic Opregion needed to access registers
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* when the controller is in D3 cold
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*/
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OperationRegion (PX01, PCI_Config, 0x00, 0xFF)
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Field (PX01, AnyAcc, NoLock, Preserve)
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{
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Offset(0x5A),
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, 6,
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PDS, 1, /* 6, Presence detect Change */
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Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */
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, 2,
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L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
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L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
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Offset(0xF4), /* BLKPLLEN */
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, 10,
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BPLL, 1,
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}
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OperationRegion (PX02, PCI_Config, 0x338, 0x4)
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Field (PX02, AnyAcc, NoLock, Preserve)
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{
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, 26,
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BDQA, 1 /* BLKDQDA */
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}
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PowerResource (PXP, 0, 0)
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{
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/* Define the PowerResource for PCIe slot */
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Method (_STA, 0, Serialized)
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{
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Store (PDS, PDST)
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If (LEqual (PDS, 1)) {
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Return (0xf)
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} Else {
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Return (0)
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}
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}
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Method (_ON, 0, Serialized)
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{
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If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
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/* Enter this condition if device
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* is connected
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*/
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/* De-assert PERST */
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\_SB.PCI0.PRDA (\PRT0)
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Store (0, BDQA) /* Set BLKDQDA to 0 */
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Store (0, BPLL) /* Set BLKPLLEN to 0 */
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/* Set L23_Rdy to Detect Transition
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* (L23R2DT)
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*/
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Store (1, L23R)
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Sleep (16)
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Store (0, Local0)
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/* Delay for transition Detect
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* and link to train
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*/
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While (L23R) {
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If (Lgreater (Local0, 4)) {
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Break
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}
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Sleep (16)
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Increment (Local0)
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}
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} /* End PDS condition check */
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}
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Method (_OFF, 0, Serialized)
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{
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/* Set L23_Rdy Entry Request (L23ER) */
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If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
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/* enter this condition if device
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* is connected
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*/
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Store (1, L23E)
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Sleep (16)
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Store (0, Local0)
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While (L23E) {
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If (Lgreater (Local0, 4)) {
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Break
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}
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Sleep (16)
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Increment (Local0)
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}
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Store (1, BDQA) /* Set BLKDQDA to 1 */
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Store (1, BPLL) /* Set BLKPLLEN to 1 */
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/* Assert PERST */
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\_SB.PCI0.PRAS (\PRT0)
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} /* End PDS condition check */
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} /* End of Method_OFF */
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} /* End PXP */
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Name(_PR0, Package() { PXP })
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Name(_PR3, Package() { PXP })
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}
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@ -17,6 +17,9 @@
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#include <soc/gpe.h>
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/* PCIE device */
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#include "pcie.asl"
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/* LPSS device */
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#include "lpss.asl"
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@ -116,6 +116,9 @@ struct soc_intel_apollolake_config {
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/* SLP S3 minimum assertion width. */
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int slp_s3_assertion_width_usecs;
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/* GPIO pin for PERST_0 */
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uint16_t prt0_gpio;
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};
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#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
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@ -414,6 +414,9 @@
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#define LPC_CLKRUNB 243
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#define LPC_FRAMEB 244
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/* PERST_0 not defined */
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#define GPIO_PRT0_UDEF 0xFF
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#define TOTAL_PADS 245
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#define N_OFFSET GPIO_0
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#define NW_OFFSET GPIO_187
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@ -38,7 +38,8 @@ typedef struct global_nvs_t {
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uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */
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uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */
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uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */
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uint8_t unused[219];
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uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */
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uint8_t unused[215];
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/* ChromeOS specific (0x100 - 0xfff) */
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chromeos_acpi_t chromeos;
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