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soc/intel/xeon_sp/acpi: Move ACPI macros to a header file 

Move ACPI macros to a header file to be used in multiple
ASL files.

This could be moved to intel/common in the future to reduce
the amount of duplicate ASL code.

Tested by checking build/dsdt.asl doesn't change.

Change-Id: Id2441763fe335154048c9a584a227a18e8c5391c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Marc Jones 2020-09-23 17:43:28 -06:00 committed by Marc Jones
parent b89624c558
commit efb583a6e9
3 changed files with 78 additions and 67 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
src/soc/intel/xeon_sp/acpi/pci_irqs.asl
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@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/acpi_asl.h>
/*
* Refer to Intel® C620 Series Chipset Platform Controller Hub EDS section 20.11
* CONFIG_PCR_BASE_ADDRESS 0xfd000000 0x3100
@ -42,49 +44,6 @@ Alias (PRSA, PRSF)
Alias (PRSA, PRSG)
Alias (PRSA, PRSH)
#define MAKE_LINK_DEV(id,uid) \
Device (LNK##id) \
{ \
Name (_HID, EISAID ("PNP0C0F")) \
Name (_UID, ##uid) \
Method (_PRS, 0, NotSerialized) \
{ \
Return (PRS##id) \
} \
Method (_CRS, 0, Serialized) \
{ \
Name (RTLA, ResourceTemplate () \
{ \
IRQ (Level, ActiveLow, Shared) {} \
}) \
CreateWordField (RTLA, 1, IRQ0) \
Store (Zero, IRQ0) \
\
/* Set the bit from PIRQ Routing Register */ \
ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \
Return (RTLA) \
} \
Method (_SRS, 1, Serialized) \
{ \
CreateWordField (Arg0, 1, IRQ0) \
FindSetRightBit (IRQ0, Local0) \
Decrement (Local0) \
Store (Local0, ^^PIR##id) \
} \
Method (_STA, 0, Serialized) \
{ \
If (And (^^PIR##id, ^^IREN)) { \
Return (0x9) \
} Else { \
Return (0xb) \
} \
} \
Method (_DIS, 0, Serialized) \
{ \
Or (^^PIR##id, ^^IREN, ^^PIR##id) \
} \
}
MAKE_LINK_DEV(A,1)
MAKE_LINK_DEV(B,2)
MAKE_LINK_DEV(C,3)

26
src/soc/intel/xeon_sp/acpi/uncore_irq.asl
View File

@ -1,35 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/acpi_asl.h>
/*
* Uncore devices PCI interrupt routing packages.
* See ACPI spec 6.2.13 _PRT (PCI routing table) for details.
* The mapping fields ae Address, Pin, Source, Source Index.
*/
#define GEN_PCIE_LEGACY_IRQ() \
Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \
Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, \
Package () { 0x0002FFFF, 0x02, LNKC, 0x00 }, \
Package () { 0x0003FFFF, 0x03, LNKD, 0x00 }
#define GEN_UNCORE_LEGACY_IRQ(dev) \
Package () { ##dev, 0x00, LNKA, 0x00 }, \
Package () { ##dev, 0x01, LNKB, 0x00 }, \
Package () { ##dev, 0x02, LNKC, 0x00 }, \
Package () { ##dev, 0x03, LNKD, 0x00 }
#define GEN_PCIE_IOAPIC_IRQ(irq1, irq2, irq3, irq4) \
Package () { 0x0000FFFF, 0x00, 0x00, ##irq1 }, \
Package () { 0x0001FFFF, 0x01, 0x00, ##irq2 }, \
Package () { 0x0002FFFF, 0x02, 0x00, ##irq3 }, \
Package () { 0x0003FFFF, 0x03, 0x00, ##irq4 }
#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \
Package () { ##dev, 0x00, 0x00, ##irq1 }, \
Package () { ##dev, 0x01, 0x00, ##irq2 }, \
Package () { ##dev, 0x02, 0x00, ##irq3 }, \
Package () { ##dev, 0x03, 0x00, ##irq4 }
// Socket 0, IIOStack 0 device legacy interrupt routing
Name (PR00, Package ()
{

74
src/soc/intel/xeon_sp/include/soc/acpi_asl.h Normal file
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@ -0,0 +1,74 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef _SOC_ACPI_ASL_H_
#define _SOC_ACPI_ASL_H_
#define GEN_PCIE_LEGACY_IRQ() \
Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \
Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, \
Package () { 0x0002FFFF, 0x02, LNKC, 0x00 }, \
Package () { 0x0003FFFF, 0x03, LNKD, 0x00 }
#define GEN_UNCORE_LEGACY_IRQ(dev) \
Package () { ##dev, 0x00, LNKA, 0x00 }, \
Package () { ##dev, 0x01, LNKB, 0x00 }, \
Package () { ##dev, 0x02, LNKC, 0x00 }, \
Package () { ##dev, 0x03, LNKD, 0x00 }
#define GEN_PCIE_IOAPIC_IRQ(irq1, irq2, irq3, irq4) \
Package () { 0x0000FFFF, 0x00, 0x00, ##irq1 }, \
Package () { 0x0001FFFF, 0x01, 0x00, ##irq2 }, \
Package () { 0x0002FFFF, 0x02, 0x00, ##irq3 }, \
Package () { 0x0003FFFF, 0x03, 0x00, ##irq4 }
#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \
Package () { ##dev, 0x00, 0x00, ##irq1 }, \
Package () { ##dev, 0x01, 0x00, ##irq2 }, \
Package () { ##dev, 0x02, 0x00, ##irq3 }, \
Package () { ##dev, 0x03, 0x00, ##irq4 }
#define MAKE_LINK_DEV(id,uid) \
Device (LNK##id) \
{ \
Name (_HID, EISAID ("PNP0C0F")) \
Name (_UID, ##uid) \
Method (_PRS, 0, NotSerialized) \
{ \
Return (PRS##id) \
} \
Method (_CRS, 0, Serialized) \
{ \
Name (RTLA, ResourceTemplate () \
{ \
IRQ (Level, ActiveLow, Shared) {} \
}) \
CreateWordField (RTLA, 1, IRQ0) \
Store (Zero, IRQ0) \
\
/* Set the bit from PIRQ Routing Register */ \
ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \
Return (RTLA) \
} \
Method (_SRS, 1, Serialized) \
{ \
CreateWordField (Arg0, 1, IRQ0) \
FindSetRightBit (IRQ0, Local0) \
Decrement (Local0) \
Store (Local0, ^^PIR##id) \
} \
Method (_STA, 0, Serialized) \
{ \
If (And (^^PIR##id, ^^IREN)) { \
Return (0x9) \
} Else { \
Return (0xb) \
} \
} \
Method (_DIS, 0, Serialized) \
{ \
Or (^^PIR##id, ^^IREN, ^^PIR##id) \
} \
}
#endif