src/mainboard: Use 'const' to set pnp_devfn_t statically
Change-Id: I50ac6914fadc02491df2eccb437eada89fd12b82 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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6 changed files with 8 additions and 12 deletions
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@ -24,8 +24,8 @@ static void sbxxx_enable_48mhzout(void)
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static void superio_init_m(void)
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static void superio_init_m(void)
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{
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{
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pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
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const pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
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pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
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const pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
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ite_kill_watchdog(gpio);
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ite_kill_watchdog(gpio);
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ite_enable_serial(uart, CONFIG_TTYS0_BASE);
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ite_enable_serial(uart, CONFIG_TTYS0_BASE);
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@ -34,7 +34,7 @@ static void superio_init_m(void)
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static void superio_init_m_pro(void)
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static void superio_init_m_pro(void)
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{
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{
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pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1);
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const pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1);
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nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE);
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nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE);
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}
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}
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@ -66,9 +66,7 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
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void bootblock_mainboard_early_init(void)
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void bootblock_mainboard_early_init(void)
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{
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{
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pnp_devfn_t dev;
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const pnp_devfn_t dev = PNP_DEV(0x4e, 0x00);
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dev = PNP_DEV(0x4e, 0x00);
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pnp_enter_ext_func_mode(dev);
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pnp_enter_ext_func_mode(dev);
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pnp_write_config(dev, 0x02, 0x0e); // UART power
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pnp_write_config(dev, 0x02, 0x0e); // UART power
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@ -35,7 +35,7 @@ void bootblock_mainboard_early_init(void)
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{
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{
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int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */
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int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */
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int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */
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int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */
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pnp_devfn_t dev = PNP_DEV(0x2e, 0x9);
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const pnp_devfn_t dev = PNP_DEV(0x2e, 0x9);
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pnp_enter_conf_state(dev);
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pnp_enter_conf_state(dev);
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pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */
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pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */
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pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */
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pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */
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@ -22,7 +22,7 @@ void mainboard_lpc_decode(void)
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static void early_superio_config(void)
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static void early_superio_config(void)
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{
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{
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int timeout = 100000;
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int timeout = 100000;
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pnp_devfn_t dev = PNP_DEV(0x2e, 3);
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const pnp_devfn_t dev = PNP_DEV(0x2e, 3);
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pnp_write_config(dev, 0x29, 0xa0);
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pnp_write_config(dev, 0x29, 0xa0);
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@ -22,7 +22,7 @@ void mainboard_lpc_decode(void)
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static void early_superio_config(void)
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static void early_superio_config(void)
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{
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{
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int timeout = 100000;
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int timeout = 100000;
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pnp_devfn_t dev = PNP_DEV(0x2e, 3);
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const pnp_devfn_t dev = PNP_DEV(0x2e, 3);
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pnp_write_config(dev, 0x29, 0x06);
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pnp_write_config(dev, 0x29, 0x06);
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@ -35,9 +35,7 @@ void mainboard_lpc_decode(void)
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void bootblock_mainboard_early_init(void)
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void bootblock_mainboard_early_init(void)
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{
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{
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pnp_devfn_t dev;
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const pnp_devfn_t dev = PNP_DEV(0x2e, 0x00);
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dev = PNP_DEV(0x2e, 0x00);
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pnp_enter_conf_state(dev);
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pnp_enter_conf_state(dev);
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pnp_write_config(dev, 0x01, 0x94); /* Extended Parport modes */
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pnp_write_config(dev, 0x01, 0x94); /* Extended Parport modes */
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