mb/intel/adlrvp: Add initial ADL-P mainboard code

List of changes:
1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig
2. Add minimum code to make ADL-P RVP build successfully
3. Mainly bootblock and verstage code added to reach till verstage
4. Add support for 2 mainboards as ADL-P board with default EC (Windows
SKU) and Chrome EC (Chrome SKU)
5. Add empty dsdt.asl to avoid compilation error

TEST=Able to build and boot ADL-P RVP till romstage early.

Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/intel/adlrvp/Kconfig

@@ -0,0 +1,86 @@
+if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_32768
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_HAS_CHROMEOS
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_INTEL_SOUNDWIRE
+	select DRIVERS_USB_ACPI
+	select DRIVERS_SPI_ACPI
+	select SOC_INTEL_ALDERLAKE
+
+config CHROMEOS
+	bool
+	default y
+	select GBB_FLAG_FORCE_DEV_SWITCH_ON
+	select GBB_FLAG_FORCE_DEV_BOOT_USB
+	select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
+	select GBB_FLAG_FORCE_MANUAL_RECOVERY
+	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+	select HAS_RECOVERY_MRC_CACHE
+	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+
+config MAINBOARD_DIR
+	string
+	default "intel/adlrvp"
+
+config VARIANT_DIR
+	string
+	default "adlrvp_p"
+
+config GBB_HWID
+	string
+	depends on CHROMEOS
+	default "ADLRVPP"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "adlrvp"
+
+config MAINBOARD_FAMILY
+	string
+	default "Intel_adlrvp"
+
+config DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+choice
+	prompt "ON BOARD EC"
+	default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P
+	default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC
+	help
+	  This option allows you to select the on board EC to use.
+	  Select whether the board has Intel EC or Chrome EC
+
+config ADL_CHROME_EC
+	bool "Chrome EC"
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_ESPI
+	select EC_GOOGLE_CHROMEEC_BOARDID
+	select EC_ACPI
+
+config ADL_INTEL_EC
+	bool "Intel EC"
+	select EC_ACPI
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+endchoice
+
+config VBOOT
+	select VBOOT_LID_SWITCH
+	select VBOOT_MOCK_SECDATA
+	select HAS_RECOVERY_MRC_CACHE
+	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+
+config UART_FOR_CONSOLE
+	int
+	default 0
+endif

src/mainboard/intel/adlrvp/Kconfig.name

@@ -0,0 +1,8 @@
+config BOARD_INTEL_ADLRVP_P
+	bool "Alderlake-P RVP"
+	select DRIVERS_UART_8250IO
+	select MAINBOARD_USES_IFD_EC_REGION
+
+config BOARD_INTEL_ADLRVP_P_EXT_EC
+	bool "Alderlake-P RVP with Chrome EC"
+	select INTEL_LPSS_UART_FOR_CONSOLE

src/mainboard/intel/adlrvp/Makefile.inc

@@ -0,0 +1,15 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+subdirs-y += variants/$(VARIANT_DIR)

src/mainboard/intel/adlrvp/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Alderlake rvp
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/intel/adlrvp/bootblock.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+
+void bootblock_mainboard_init(void)
+{
+	variant_configure_early_gpio_pads();
+}

src/mainboard/intel/adlrvp/chromeos.c

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{-1, ACTIVE_HIGH, 0, "EC in RW"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES)
+int get_lid_switch(void)
+{
+	/* Lid always open */
+	return 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}
+#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
+
+int get_write_protect_state(void)
+{
+	/* No write protect */
+	return 0;
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	const struct cros_gpio *gpios;
+	size_t num;
+
+	gpios = variant_cros_gpios(&num);
+	chromeos_acpi_gpio_generate(gpios, num);
+}

src/mainboard/intel/adlrvp/chromeos.fmd

@@ -0,0 +1,44 @@
+FLASH@0xfe000000 32M {
+	SI_ALL 0x1081000 {
+		SI_DESC 0x1000
+		SI_EC 0x80000
+		SI_ME
+	}
+	SI_BIOS@0x1400000 0xc00000 {
+		RW_SECTION_A 0x368000 {
+			VBLOCK_A 0x10000
+			FW_MAIN_A(CBFS) 0x357fc0
+			RW_FWID_A 0x40
+		}
+		RW_SECTION_B 0x368000 {
+			VBLOCK_B 0x10000
+			FW_MAIN_B(CBFS) 0x357fc0
+			RW_FWID_B 0x40
+		}
+		RW_MISC 0x30000 {
+			UNIFIED_MRC_CACHE 0x20000 {
+				RECOVERY_MRC_CACHE 0x10000
+				RW_MRC_CACHE 0x10000
+			}
+			RW_ELOG(PRESERVE) 0x4000
+			RW_SHARED 0x4000 {
+				SHARED_DATA 0x2000
+				VBLOCK_DEV 0x2000
+			}
+			RW_VPD(PRESERVE) 0x2000
+			RW_NVRAM(PRESERVE) 0x6000
+		}
+		# RW_LEGACY needs to be minimum of 1MB
+		RW_LEGACY(CBFS) 0x100000
+		WP_RO {
+			RO_VPD(PRESERVE) 0x4000
+			RO_SECTION {
+				FMAP 0x800
+				RO_FRID 0x40
+				RO_FRID_PAD 0x7c0
+				GBB 0x3000
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}

src/mainboard/intel/adlrvp/dsdt.asl

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		/* DSDT revision: ACPI v2.0 and up */
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	/* OEM revision */
+)
+{
+
+}

src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc

@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += early_gpio.c

src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb

@@ -0,0 +1,111 @@
+chip soc/intel/alderlake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+	register "gen4_dec" = "0x000c0081"
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Graphics
+		device pci 04.0 on  end # DPTF
+		device pci 05.0 on  end # IPU
+		device pci 06.0 on  end # PEG60
+		device pci 07.0 off end # TBT_PCIe0
+		device pci 07.1 off end # TBT_PCIe1
+		device pci 07.2 off end # TBT_PCIe2
+		device pci 07.3 off end # TBT_PCIe3
+		device pci 08.0 off end # GNA
+		device pci 09.0 off end # NPK
+		device pci 0a.0 off end # Crash-log SRAM
+		device pci 0d.0 on  end # USB xHCI
+		device pci 0d.1 off end # USB xDCI (OTG)
+		device pci 0d.2 off end # TBT DMA0
+		device pci 0d.3 off end # TBT DMA1
+		device pci 0e.0 off end # VMD
+		device pci 10.0 off end
+		device pci 10.1 off end
+		device pci 10.2 on  end # CNVi: BT
+		device pci 10.6 off end # THC0
+		device pci 10.7 off end # THC1
+		device pci 11.0 off end
+		device pci 11.1 off end
+		device pci 11.2 off end
+		device pci 11.3 off end
+		device pci 11.4 off end
+		device pci 11.5 off end
+		device pci 12.0 off end # SensorHUB
+		device pci 12.5 off end
+		device pci 12.6 off end # GSPI2
+		device pci 13.0 off end # GSPI3
+		device pci 13.1 off end
+		device pci 14.0 on
+			chip drivers/usb/acpi
+				register "desc" = ""Root Hub""
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 on
+					chip drivers/usb/acpi
+						register "desc" = ""Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.9 on end
+					end
+				end
+			end
+		end # USB3.1 xHCI
+		device pci 14.1 off end # USB3.1 xDCI
+		device pci 14.2 off end # Shared RAM
+		chip drivers/intel/wifi
+			register "wake" = "GPE0_PME_B0"
+			device pci 14.3 on end # CNVi: WiFi
+		end
+		device pci 15.0 on  end	# I2C0
+		device pci 15.1 on  end # I2C1
+		device pci 15.2 on  end # I2C2
+		device pci 15.3 on  end # I2C3
+		device pci 16.0 on  end # HECI1
+		device pci 16.1 off end # HECI2
+		device pci 16.2 off end # CSME
+		device pci 16.3 off end # CSME
+		device pci 16.4 off end # HECI3
+		device pci 16.5 off end # HECI4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 off end # I2C4
+		device pci 19.1 on  end # I2C5
+		device pci 19.2 on  end # UART2
+		device pci 1c.0 on  end # RP1
+		device pci 1c.1 on  end # RP2
+		device pci 1c.2 on  end # RP3
+		device pci 1c.3 on  end # RP4
+		device pci 1c.4 on  end # RP5
+		device pci 1c.5 on  end # RP6
+		device pci 1c.6 on  end # RP7
+		device pci 1c.7 on  end # RP8
+		device pci 1d.0 on  end # RP9
+		device pci 1d.1 on  end # RP10
+		device pci 1d.2 on  end # RP11
+		device pci 1d.3 on  end # RP12
+		device pci 1e.0 off end # UART0
+		device pci 1e.1 off end # UART1
+		device pci 1e.2 off end # GSPI0
+		device pci 1e.3 off end # GSPI1
+		device pci 1f.0 on  end # eSPI
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 hidden  end # PMC
+		device pci 1f.3 on
+			chip drivers/intel/soundwire
+				device generic 0 on
+				end
+			end
+		end # Intel Audio SNDW
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # SPI
+		device pci 1f.6 off end # GbE
+		device pci 1f.7 off end # TH
+	end
+end

src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <soc/gpio.h>
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* WWAN_RST# */
+	PAD_CFG_GPO(GPP_E10, 0, PLTRST),
+	/* WWAN_PWR_EN */
+	PAD_CFG_GPO(GPP_E13, 1, DEEP),
+};
+
+void variant_configure_early_gpio_pads(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI	GPE0_ESPI
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+/* EC sync IRQ */
+#define EC_SYNC_IRQ	GPP_A15_IRQ
+
+#endif /* __BASEBOARD_GPIO_H__ */

src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* The next set of functions return the gpio table and fill in the number of
+ * entries for each table. */
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+void variant_configure_early_gpio_pads(void);
+
+#endif /*__BASEBOARD_VARIANTS_H__ */