mb/intel/adlrvp: Add initial ADL-P mainboard code
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU) 5. Add empty dsdt.asl to avoid compilation error TEST=Able to build and boot ADL-P RVP till romstage early. Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik
parent
58222d156a
commit
efc40090f5
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if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_32768
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_CHROMEOS
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_GENERIC
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select DRIVERS_INTEL_SOUNDWIRE
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select DRIVERS_USB_ACPI
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select DRIVERS_SPI_ACPI
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select SOC_INTEL_ALDERLAKE
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config CHROMEOS
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bool
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default y
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
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select GBB_FLAG_FORCE_MANUAL_RECOVERY
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select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
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select HAS_RECOVERY_MRC_CACHE
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select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
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config MAINBOARD_DIR
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string
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default "intel/adlrvp"
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config VARIANT_DIR
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string
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default "adlrvp_p"
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config GBB_HWID
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string
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depends on CHROMEOS
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default "ADLRVPP"
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config MAINBOARD_PART_NUMBER
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string
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default "adlrvp"
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config MAINBOARD_FAMILY
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string
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default "Intel_adlrvp"
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config DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config DIMM_SPD_SIZE
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int
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default 512
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choice
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prompt "ON BOARD EC"
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default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P
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default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC
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help
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This option allows you to select the on board EC to use.
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Select whether the board has Intel EC or Chrome EC
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config ADL_CHROME_EC
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bool "Chrome EC"
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_ESPI
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_ACPI
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config ADL_INTEL_EC
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bool "Intel EC"
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select EC_ACPI
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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endchoice
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config VBOOT
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select VBOOT_LID_SWITCH
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select VBOOT_MOCK_SECDATA
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select HAS_RECOVERY_MRC_CACHE
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select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
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config UART_FOR_CONSOLE
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int
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default 0
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endif
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@ -0,0 +1,8 @@
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config BOARD_INTEL_ADLRVP_P
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bool "Alderlake-P RVP"
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select DRIVERS_UART_8250IO
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select MAINBOARD_USES_IFD_EC_REGION
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config BOARD_INTEL_ADLRVP_P_EXT_EC
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bool "Alderlake-P RVP with Chrome EC"
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select INTEL_LPSS_UART_FOR_CONSOLE
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += bootblock.c
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bootblock-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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subdirs-y += variants/$(VARIANT_DIR)
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Vendor name: Intel
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Board name: Alderlake rvp
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Category: eval
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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void bootblock_mainboard_init(void)
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{
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variant_configure_early_gpio_pads();
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{-1, ACTIVE_HIGH, 0, "EC in RW"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES)
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int get_lid_switch(void)
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{
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/* Lid always open */
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return 1;
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}
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int get_recovery_mode_switch(void)
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{
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return 0;
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}
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#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
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int get_write_protect_state(void)
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{
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/* No write protect */
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return 0;
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}
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void mainboard_chromeos_acpi_generate(void)
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{
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const struct cros_gpio *gpios;
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size_t num;
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gpios = variant_cros_gpios(&num);
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chromeos_acpi_gpio_generate(gpios, num);
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}
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FLASH@0xfe000000 32M {
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SI_ALL 0x1081000 {
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SI_DESC 0x1000
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SI_EC 0x80000
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SI_ME
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}
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SI_BIOS@0x1400000 0xc00000 {
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RW_SECTION_A 0x368000 {
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VBLOCK_A 0x10000
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FW_MAIN_A(CBFS) 0x357fc0
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RW_FWID_A 0x40
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}
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RW_SECTION_B 0x368000 {
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VBLOCK_B 0x10000
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FW_MAIN_B(CBFS) 0x357fc0
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RW_FWID_B 0x40
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}
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RW_MISC 0x30000 {
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UNIFIED_MRC_CACHE 0x20000 {
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RECOVERY_MRC_CACHE 0x10000
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RW_MRC_CACHE 0x10000
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}
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RW_ELOG(PRESERVE) 0x4000
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RW_SHARED 0x4000 {
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SHARED_DATA 0x2000
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VBLOCK_DEV 0x2000
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}
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RW_VPD(PRESERVE) 0x2000
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RW_NVRAM(PRESERVE) 0x6000
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}
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# RW_LEGACY needs to be minimum of 1MB
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RW_LEGACY(CBFS) 0x100000
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WP_RO {
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RO_VPD(PRESERVE) 0x4000
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RO_SECTION {
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FMAP 0x800
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RO_FRID 0x40
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RO_FRID_PAD 0x7c0
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GBB 0x3000
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COREBOOT(CBFS)
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}
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}
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}
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, /* DSDT revision: ACPI v2.0 and up */
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 /* OEM revision */
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)
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{
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}
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += early_gpio.c
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chip soc/intel/alderlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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register "gen4_dec" = "0x000c0081"
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Graphics
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device pci 04.0 on end # DPTF
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device pci 05.0 on end # IPU
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device pci 06.0 on end # PEG60
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device pci 07.0 off end # TBT_PCIe0
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device pci 07.1 off end # TBT_PCIe1
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device pci 07.2 off end # TBT_PCIe2
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device pci 07.3 off end # TBT_PCIe3
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device pci 08.0 off end # GNA
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device pci 09.0 off end # NPK
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device pci 0a.0 off end # Crash-log SRAM
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device pci 0d.0 on end # USB xHCI
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device pci 0d.1 off end # USB xDCI (OTG)
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device pci 0d.2 off end # TBT DMA0
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device pci 0d.3 off end # TBT DMA1
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device pci 0e.0 off end # VMD
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device pci 10.0 off end
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device pci 10.1 off end
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device pci 10.2 on end # CNVi: BT
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device pci 10.6 off end # THC0
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device pci 10.7 off end # THC1
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device pci 11.0 off end
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device pci 11.1 off end
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device pci 11.2 off end
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device pci 11.3 off end
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device pci 11.4 off end
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device pci 11.5 off end
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device pci 12.0 off end # SensorHUB
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device pci 12.5 off end
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device pci 12.6 off end # GSPI2
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device pci 13.0 off end # GSPI3
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device pci 13.1 off end
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device pci 14.0 on
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chip drivers/usb/acpi
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register "desc" = ""Root Hub""
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register "type" = "UPC_TYPE_HUB"
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device usb 0.0 on
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chip drivers/usb/acpi
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register "desc" = ""Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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device usb 2.9 on end
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end
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end
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end
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end # USB3.1 xHCI
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device pci 14.1 off end # USB3.1 xDCI
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device pci 14.2 off end # Shared RAM
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chip drivers/intel/wifi
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register "wake" = "GPE0_PME_B0"
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device pci 14.3 on end # CNVi: WiFi
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end
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device pci 15.0 on end # I2C0
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device pci 15.1 on end # I2C1
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device pci 15.2 on end # I2C2
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device pci 15.3 on end # I2C3
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device pci 16.0 on end # HECI1
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device pci 16.1 off end # HECI2
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device pci 16.2 off end # CSME
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device pci 16.3 off end # CSME
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device pci 16.4 off end # HECI3
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device pci 16.5 off end # HECI4
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device pci 17.0 on end # SATA
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device pci 19.0 off end # I2C4
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device pci 19.1 on end # I2C5
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device pci 19.2 on end # UART2
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device pci 1c.0 on end # RP1
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device pci 1c.1 on end # RP2
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device pci 1c.2 on end # RP3
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device pci 1c.3 on end # RP4
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device pci 1c.4 on end # RP5
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device pci 1c.5 on end # RP6
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device pci 1c.6 on end # RP7
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device pci 1c.7 on end # RP8
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device pci 1d.0 on end # RP9
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device pci 1d.1 on end # RP10
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device pci 1d.2 on end # RP11
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device pci 1d.3 on end # RP12
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device pci 1e.0 off end # UART0
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device pci 1e.1 off end # UART1
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device pci 1e.2 off end # GSPI0
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device pci 1e.3 off end # GSPI1
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device pci 1f.0 on end # eSPI
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device pci 1f.1 on end # P2SB
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device pci 1f.2 hidden end # PMC
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device pci 1f.3 on
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chip drivers/intel/soundwire
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device generic 0 on
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end
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end
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end # Intel Audio SNDW
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # SPI
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device pci 1f.6 off end # GbE
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device pci 1f.7 off end # TH
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end
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end
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* WWAN_RST# */
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PAD_CFG_GPO(GPP_E10, 0, PLTRST),
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/* WWAN_PWR_EN */
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PAD_CFG_GPO(GPP_E13, 1, DEEP),
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};
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void variant_configure_early_gpio_pads(void)
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{
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __BASEBOARD_GPIO_H__
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#define __BASEBOARD_GPIO_H__
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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/* eSPI virtual wire reporting */
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#define EC_SCI_GPI GPE0_ESPI
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/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
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#define GPE_EC_WAKE GPE0_LAN_WAK
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/* EC sync IRQ */
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#define EC_SYNC_IRQ GPP_A15_IRQ
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#endif /* __BASEBOARD_GPIO_H__ */
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@ -0,0 +1,16 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __BASEBOARD_VARIANTS_H__
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#define __BASEBOARD_VARIANTS_H__
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#include <soc/gpio.h>
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#include <stdint.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* The next set of functions return the gpio table and fill in the number of
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* entries for each table. */
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const struct cros_gpio *variant_cros_gpios(size_t *num);
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void variant_configure_early_gpio_pads(void);
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#endif /*__BASEBOARD_VARIANTS_H__ */
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