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mb/intel/kblrvp8: Add KBLRVP8 support 

Add the config for setting SPD DIMM size to 512 bytes
for KBLRVP8 with DDR4 memory. Configure the DIMM1 memory
SPD data for channel0 and channel1. Set the UserBd UPD to
BOARD_TYPE_DESKTOP for kblrvp8.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I985968d331991884050c3920ec9798cd4cb371c7
Reviewed-on: https://review.coreboot.org/25194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
This commit is contained in:
V Sowmya 2018-03-15 21:38:30 +05:30 committed by Patrick Georgi
parent 57afc5e0f2
commit efce854fc6
2 changed files with 13 additions and 4 deletions
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3
src/mainboard/intel/kblrvp/Kconfig
View File

@ -98,4 +98,7 @@ config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0xd00
config DIMM_SPD_SIZE
int
default 512 if BOARD_INTEL_KBLRVP8 #DDR4
endif

12
src/mainboard/intel/kblrvp/romstage.c
View File

@ -49,7 +49,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
/* Memory leak is ok since we have memory mapped boot media */
mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
} else { /* for CONFIG_BOARD_INTEL_KBLRVP7 */
} else { /* CONFIG_BOARD_INTEL_KBLRVP7 and CONFIG_BOARD_INTEL_KBLRVP8 */
struct spd_block blk = {
.addr_map = { 0x50, 0x51, 0x52, 0x53, },
};
@ -57,9 +57,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
mem_cfg->DqPinsInterleaved = 1;
get_spd_smbus(&blk);
mem_cfg->MemorySpdDataLen = blk.len;
mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0];
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2];
if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) {
mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1];
mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
}
mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
}
mupd->FspmTestConfig.DmiVc1 = 1;
if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8))
mem_cfg->UserBd = BOARD_TYPE_DESKTOP;
}