soc/intel/apollolake: Configure PCIe root port #1 for APL WiFi
APL uses PCIe root port 1 (PCIe ID 14.0) for discrete PCIe wifi card. BUG=None BRANCH=None TEST=Use Stone Peak discrete wifi card and test s0ix. Change-Id: Ia81722f4533916fe93009a73d86765e5de9dab08 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/25637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -13,114 +13,12 @@
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* GNU General Public License for more details.
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*/
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/* PCIe Ports */
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Device (RP01)
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{
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Name (_ADR, 0x00140000)
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Name (_DDN, "PCIe-B 0")
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Name (PDST, 0) /* present Detect status */
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/* lowest D-state supported by
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* PCIe root port during S0 state
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*/
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Name (_S0W, 4)
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/* Dynamic Opregion needed to access registers
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* when the controller is in D3 cold
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*/
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OperationRegion (PX01, PCI_Config, 0x00, 0xFF)
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Field (PX01, AnyAcc, NoLock, Preserve)
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{
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Offset(0x5A),
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, 6,
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PDS, 1, /* 6, Presence detect Change */
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Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */
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, 2,
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L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
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L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
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Offset(0xF4), /* BLKPLLEN */
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, 10,
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BPLL, 1,
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}
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OperationRegion (PX02, PCI_Config, 0x338, 0x4)
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Field (PX02, AnyAcc, NoLock, Preserve)
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{
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, 26,
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BDQA, 1 /* BLKDQDA */
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}
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PowerResource (PXP, 0, 0)
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{
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/* Define the PowerResource for PCIe slot */
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Method (_STA, 0, Serialized)
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{
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Store (PDS, PDST)
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If (LEqual (PDS, 1)) {
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Return (0xf)
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} Else {
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Return (0)
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}
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}
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Method (_ON, 0, Serialized)
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{
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If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
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/* Enter this condition if device
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* is connected
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*/
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/* De-assert PERST */
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\_SB.PCI0.PRDA (\PRT0)
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Store (0, BDQA) /* Set BLKDQDA to 0 */
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Store (0, BPLL) /* Set BLKPLLEN to 0 */
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/* Set L23_Rdy to Detect Transition
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* (L23R2DT)
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*/
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Store (1, L23R)
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Sleep (16)
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Store (0, Local0)
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/* Delay for transition Detect
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* and link to train
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*/
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While (L23R) {
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If (Lgreater (Local0, 4)) {
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Break
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}
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Sleep (16)
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Increment (Local0)
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}
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} /* End PDS condition check */
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}
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Method (_OFF, 0, Serialized)
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{
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/* Set L23_Rdy Entry Request (L23ER) */
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If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
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/* enter this condition if device
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* is connected
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*/
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Store (1, L23E)
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Sleep (16)
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Store (0, Local0)
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While (L23E) {
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If (Lgreater (Local0, 4)) {
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Break
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}
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Sleep (16)
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Increment (Local0)
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}
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Store (1, BDQA) /* Set BLKDQDA to 1 */
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Store (1, BPLL) /* Set BLKPLLEN to 1 */
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/* Assert PERST */
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\_SB.PCI0.PRAS (\PRT0)
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} /* End PDS condition check */
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} /* End of Method_OFF */
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} /* End PXP */
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Name(_PR0, Package() { PXP })
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Name(_PR3, Package() { PXP })
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#include "pcie_port.asl"
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}
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@ -111,7 +111,7 @@ static const char *soc_acpi_name(const struct device *dev)
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case PCH_DEVFN_SDIO:
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return "SDIO";
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/* PCIe */
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case PCH_DEVFN_PCIE1:
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case PCH_DEVFN_PCIE5:
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return "RP01";
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}
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