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mb/google/volteer/variant/lindar: Disable acoustic mitigation 

Roll back CPU slow slew rate setting to Intel default "SLEW_FAST_2"
Because baseboard modify slow slew rate setting to "SLEW_FASE_8"
for all project, but Lindar and Lillipup is using "SLEW_FAST_2",
so this setting need to roll back.

BUG=b:186140230
TEST=Build FW and boot to OS checking with CPU log.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I7de252b26c75f8dad218f3eb79a0988e60964f4c
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52620
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kevin Chang 2021-04-23 10:12:46 +08:00 committed by Nick Vaccaro
parent 1fb5395d9d
commit f005dda9dd
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/volteer/variants/lindar/overridetree.cb
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@ -57,6 +57,12 @@ chip soc/intel/tigerlake
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci,
}" }"
# Acoustic settings
register "AcousticNoiseMitigation" = "0"
register "SlowSlewRate" = "SLEW_FAST_2"
register "FastPkgCRampDisable" = "0"
device domain 0 on device domain 0 on
device ref dptf on device ref dptf on
chip drivers/intel/dptf chip drivers/intel/dptf