diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig
index 57b1762578..f07bc82320 100644
--- a/src/mainboard/google/gru/Kconfig
+++ b/src/mainboard/google/gru/Kconfig
@@ -60,10 +60,6 @@ config MAINBOARD_VENDOR
 	string
 	default "Google"
 
-config DRAM_SIZE_MB
-	int
-	default 4096
-
 config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 0x5
diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c
index 55ed79a574..7f84a2a2a1 100644
--- a/src/mainboard/google/gru/romstage.c
+++ b/src/mainboard/google/gru/romstage.c
@@ -33,9 +33,6 @@
 
 #include "pwm_regulator.h"
 
-static const uint64_t dram_size =
-	(uint64_t)min((uint64_t)CONFIG_DRAM_SIZE_MB * MiB, MAX_DRAM_ADDRESS);
-
 static void init_dvs_outputs(void)
 {
 	pwm_regulator_configure(PWM_REGULATOR_GPU, 900);
@@ -66,7 +63,8 @@ void main(void)
 
 	sdram_init(get_sdram_config());
 
-	mmu_config_range((void *)0, (uintptr_t)dram_size, CACHED_MEM);
+	mmu_config_range((void *)0, (uintptr_t)sdram_size_mb() * MiB,
+			 CACHED_MEM);
 	mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);
 	cbmem_initialize_empty();
 	run_ramstage();
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index d085e4c44e..e51cd8968d 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -1031,5 +1031,41 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params)
 
 size_t sdram_size_mb(void)
 {
-	return CONFIG_DRAM_SIZE_MB;
+	u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
+	size_t chipsize_mb = 0;
+	static size_t size_mb = 0;
+	u32 ch;
+
+	if (!size_mb) {
+		u32 sys_reg = read32(&rk3399_pmugrf->os_reg2);
+		u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg);
+
+		for (ch = 0; ch < ch_num; ch++) {
+			rank = SYS_REG_DEC_RANK(sys_reg, ch);
+			col = SYS_REG_DEC_COL(sys_reg, ch);
+			bk = SYS_REG_DEC_BK(sys_reg, ch);
+			cs0_row = SYS_REG_DEC_CS0_ROW(sys_reg, ch);
+			cs1_row = SYS_REG_DEC_CS1_ROW(sys_reg, ch);
+			bw = SYS_REG_DEC_BW(sys_reg, ch);
+			row_3_4 = SYS_REG_DEC_ROW_3_4(sys_reg, ch);
+
+			chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
+
+			if (rank > 1)
+				chipsize_mb += chipsize_mb >>
+					(cs0_row - cs1_row);
+			if (row_3_4)
+				chipsize_mb = chipsize_mb * 3 / 4;
+			size_mb += chipsize_mb;
+		}
+
+		/*
+		 * we use the 0x00000000~0xf7ffffff space
+		 * since 0xf8000000~0xffffffff is soc register space
+		 * so we reserve it
+		 */
+		size_mb = MIN(size_mb, 0xf8000000/MiB);
+	}
+
+	return size_mb;
 }
diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c
index e34ca09d06..4418a27a25 100644
--- a/src/soc/rockchip/rk3399/soc.c
+++ b/src/soc/rockchip/rk3399/soc.c
@@ -20,6 +20,7 @@
 #include <soc/addressmap.h>
 #include <soc/clock.h>
 #include <soc/display.h>
+#include <soc/sdram.h>
 #include <stddef.h>
 #include <stdlib.h>
 #include <string.h>
@@ -27,8 +28,7 @@
 
 static void soc_read_resources(device_t dev)
 {
-	ram_resource(dev, 0, (uintptr_t)_dram / KiB,
-		     min(CONFIG_DRAM_SIZE_MB * KiB, MAX_DRAM_ADDRESS / KiB));
+	ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size_mb() * KiB);
 }
 
 static void soc_init(device_t dev)