soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX

CB:41106 revealed that mb/intel/cedarisland already sets FSP-S UPD (see
CB:40735) while the required includes are still missing in CPX. Buildbot
did not fail because `ramstage.c` never was (implicitly) included.

Fix this problem by making SKX/CPX share a common ramstage header for
now by moving the one from SKX.

Test: Build cedarisland_crb

Change-Id: I9cd25edd167ec71ee98c7ffa4fa6f95ca73a75e9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>

src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h

@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
-
-#include <device/device.h>
-
-extern struct pci_operations soc_pci_ops;