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src/soc/intel/braswell/acpi/lpc.asl: Add ACPI and GPIO bases 

ACPI and GPIO base are used by LPC controller, but not reserved.
Both bases are added to the LPC device resources.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I5248694b497c4965d79dd7c25ec97592dc0dddbc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Frans Hendriks 2018-10-31 10:07:11 +01:00 committed by Patrick Georgi
parent ad19c2f58b
commit f01a15952a
1 changed files with 4 additions and 0 deletions
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src/soc/intel/braswell/acpi/lpc.asl
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@ -106,6 +106,10 @@ Device (LPCB)
IO (Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */ IO (Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
IO (Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */ IO (Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
0x1, ACPI_BASE_SIZE) /* ACPI Base */
IO (Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS,
0x1, 0xff) /* GPIO Base */
}) })
Method (_CRS, 0, NotSerialized) Method (_CRS, 0, NotSerialized)