fix constants style
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -146,12 +146,12 @@
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#define CF8F_UPPER_32BIT_SET 1 << 5
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#define CF8F_UPPER_HOI_LOI_SET 1 << 1
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#define MC_CF1017_DATA MSR_MC + 1Ah
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#define MC_CF1017_DATA MSR_MC + 0x1A
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#define CF1017_LOWER_PM1_UP_DLY_SET 1 << 8
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#define CF1017_LOWER_WR2DAT_SHIFT 0
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#define MC_CFCLK_DBUG MSR_MC + 1Dh
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#define MC_CFCLK_DBUG MSR_MC + 0x1D
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#define CFCLK_UPPER_MTST_B2B_DIS_SET 1 << 2
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#define CFCLK_UPPER_MTST_DQS_EN_SET 1 << 1
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@ -159,45 +159,45 @@
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#define CFCLK_LOWER_MASK_CKE_SET1 1 << 9
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#define CFCLK_LOWER_MASK_CKE_SET0 1 << 8
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#define CFCLK_LOWER_SDCLK_SET 0Fh << 0
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#define CFCLK_LOWER_SDCLK_SET 0x0F << 0
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#define MC_CF_RDSYNC MSR_MC + 1Fh
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#define MC_CF_RDSYNC MSR_MC + 0x1F
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/**/
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/* GLIU1 GLIU0 port2*/
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/**/
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#define GLIU1_GLD_MSR_CAP MSR_GLIU1 + 2000h
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#define GLIU1_GLD_MSR_PM MSR_GLIU1 + 2004h
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#define GLIU1_GLD_MSR_CAP MSR_GLIU1 + 0x2000
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#define GLIU1_GLD_MSR_PM MSR_GLIU1 + 0x2004
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#define GLIU1_GLD_MSR_COH MSR_GLIU1 + 80h
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#define GLIU1_GLD_MSR_COH MSR_GLIU1 + 0x80
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/**/
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/* CPU ; does not need routing instructions since we are executing there.*/
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/**/
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#define CPU_GLD_MSR_CAP 2000h
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#define CPU_GLD_MSR_CONFIG 2001h
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#define CPU_GLD_MSR_PM 2004h
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#define CPU_GLD_MSR_CAP 0x2000
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#define CPU_GLD_MSR_CONFIG 0x2001
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#define CPU_GLD_MSR_PM 0x2004
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#define CPU_GLD_MSR_DIAG 2005h
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#define CPU_GLD_MSR_DIAG 0x2005
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#define DIAG_SEL1_MODE_SHIFT 16
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#define DIAG_SEL1_SET 1 << 31
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#define DIAG_SEL0__MODE_SHIFT 0
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#define DIAG_SET0_SET 1 << 15
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#define CPU_PF_BTB_CONF 1100h
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#define CPU_PF_BTB_CONF 0x1100
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#define BTB_ENABLE_SET 1 << 0
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#define RETURN_STACK_ENABLE_SET 1 << 4
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#define CPU_PF_BTBRMA_BIST 110Ch
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#define CPU_PF_BTBRMA_BIST 0x110C
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#define CPU_XC_CONFIG 1210h
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#define CPU_XC_CONFIG 0x1210
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#define XC_CONFIG_SUSP_ON_HLT 1 << 0
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#define CPU_ID_CONFIG 1250h
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#define CPU_ID_CONFIG 0x1250
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#define ID_CONFIG_SERIAL_SET 1 << 0
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#define CPU_AC_MSR 1301h
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#define CPU_EX_BIST 1428h
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#define CPU_AC_MSR 0x1301
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#define CPU_EX_BIST 0x1428
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/*IM*/
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#define CPU_IM_CONFIG 0x1700
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