mb/google/brya: Add two sensors for DPTF functionality
Add two thermal sensors for fan and wwan for DPTF based thermal control. BRANCH=None BUG=b:181271666 TEST=None Change-Id: Idc9bd6040c9bb316ec7e314f5e9c937c75cfc95a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com>
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@ -46,8 +46,10 @@ chip soc/intel/alderlake
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DRAM""
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register "options.tsr[1].desc" = ""Charger""
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register "options.tsr[0].desc" = ""DRAM_SOC""
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register "options.tsr[1].desc" = ""Ambient""
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register "options.tsr[2].desc" = ""Charger""
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register "options.tsr[3].desc" = ""WWAN""
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# TODO: below values are initial reference values only
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## Active Policy
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@ -58,6 +60,18 @@ chip soc/intel/alderlake
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TEMP_PCT(85, 90),
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TEMP_PCT(80, 80),
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TEMP_PCT(75, 70),
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TEMP_PCT(70, 50),
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TEMP_PCT(65, 30),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_1,
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.thresholds = {
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TEMP_PCT(50, 90),
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TEMP_PCT(48, 70),
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TEMP_PCT(46, 60),
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TEMP_PCT(43, 40),
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TEMP_PCT(40, 30),
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}
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}
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}"
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@ -66,7 +80,9 @@ chip soc/intel/alderlake
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
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[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
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[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
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[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000),
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}"
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## Critical Policy
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@ -74,6 +90,8 @@ chip soc/intel/alderlake
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
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[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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